IA-32 Intel Manual Learning Note (ii) memory management in protected mode

Memory Management Overview (Management overview)

The memory management of the inter architecture can be divided into two parts: fragmentation and paging. Fragmentation provides a mechanism for providing separate code, data, and stack modules for each program or task, which ensures that multiple processes or tasks can run on the same processor without interfering with each other. The paging mechanism provides a virtual memory system in which the execution code of the program is mapped to physical memory as needed. The paging mechanism can also be used to isolate multiple tasks. In protected mode, the staging mechanism is required, and the paging mechanism is optional

The fragmentation mechanism divides the processor addressable space (that is, the linear space) into several smaller, protected address space segments. Segments can be used to load the program's code, data or stacks, or to load the system's data structures (such as TSS, LDT, etc.). When multiple processes are running on the processor, the operating system assigns each process its own segment, and the processor prescribes the boundaries of those segments, ensuring that one process does not interfere with the reading and writing of the segments of another process.

All segments in the system are within the linear address space of the processor, but only logical addresses can determine the position of one byte in a particular segment. So when the actual program accesses the memory, there is a mechanism to map the logical address to the linear address. A logical address consists of a segment selector and an offset. With the segment selector, you can uniquely locate a segment descriptor in the global/Local Descriptor List (Gdt/ldt), and each segment descriptor records the base address of a segment in a linear address space, and then adds the actual linear address by adding the offset amount.

in protected mode, the segment selector is actually a CS register, which is 16 bits. The offset is the EIP register, which is 32 bits. The above procedure is actually to map the 16-bit logical address in CS to a 32-bit linear address.

use of the segment (using segments)

The segmentation mechanism used by the Intel architecture is used to implement a variety of different system designs

Basic Flat Model only uses segmentation to protect programs. The operating system and applications can access a contiguous, non-segmented address space, which does not produce an "out of memory" exception even when there is no physical memory at the address visited

the protected flat models (Protected Flat model) are similar to the basic flat model, except that the segment length is set to the actual physical memory range, and if an attempt is made to access an address other than the actual memory, a generic protection exception is generated

The multi-segment model takes full advantage of the fragmentation mechanism, providing mandatory protection of code, data structures, and the hardware level of the program. Here, each process has its own segment descriptor and its own segment. LDT. logical AND Linear addresses (Logical and Linear address)

The logical address, relative to the offset address of the base site of the process, is used directly by the application as a logical address, without concern for the physical address of the segmented paging mechanism transformation. The logical address consists of a 16-bit segment selector (CS) and a 32-bit offset (EIP).

A linear address is a bridge between a logical address and a physical address translation. The logical address is an offset, the address in the segment descriptor is the base address, and the result of the addition is a linear address. The linear address is a 32-bit address, and the address space contains all the segments and various system tables defined for the system

The Physical address in the actual memory, that is, addressing on the address bus. If the paging mechanism is not used, then the linear address is the physical address. If the paging mechanism is used, then the page directory and the page table need to be converted to physical addresses. 32-bit machines have a total of 32 address bus, the actual physical address memory space is 4GB, that is 2 of the 32-time Square

the transition relationship between the three is as follows: Locate the segment descriptor for the segment in the GDT or LDT by the segment selector in the logical address (this step is only performed if a new segment selector is read into the segment register). Check the access permissions in the segment descriptor and the range of addresses of the segments to ensure that the segment is accessible, that is, the offset adds the segment base and offset in the segment descriptor to a linear address if no paging is used, then the linear address is the physical address, otherwise, You need to translate the linear address into a physical address based on the page directory and also the table

Segment Selector
A segment selector is a 16-bit segment identifier that does not directly point to the segment, but instead points to the segment descriptor that defines the segment. The segment selector is actually CS in Cs:eip. A segment selector contains the item index index, in 3-15 bits. Identifies the index of the corresponding segment descriptor in Gdt/ldt, when addressing the base address of the index * 8 + Gdt/ldt can be found corresponding to the segment descriptor of the TI tag, in the 2nd bit. Used to identify which descriptor descriptor to use, 0 means that gdt,1 represents the privilege level of the LDT RPL request, in 0-1 bits. Determines the privileged level of the selector. Privilege level from 0-3,0 to highest privilege level (kernel), 3 for least privileged (user)

Segment Descriptor
The segment descriptor is a 64-bit segment identifier, which occupies 8 bytes, in Gdt/ldt, where the flags and fields are limited to the length field, specifying the size of the segment. The base address domain, which refers to the segment memory of the base Address Type field, indicates the type of segment or gate, determines the extent of the segment permission and growth direction S (descriptor type) flag, determines whether the segment descriptor is a system descriptor or code (s marked as 0 o'clock), data segment identifier (s marked as 1 o'clock) DPL (Descriptor privilege level) field, Indicates the privileged level of the segment, with a privilege level from 0-3. 0 is the highest privileged level, DPL is used to control the access P (segment presence) flag for the segment, indicating whether the segment is in memory (1 means in memory, 0 means not in memory) d/b (default operand size/default stack pointer size/upper) flag, according to which the segment descriptor refers to an executable code snippet, A scaled-down data segment is also a stack segment, which accomplishes a different function G (granularity) flag, which determines the increment of the segment's limit extension is available and reserved for S

The first item in the GDT is empty and cannot be used, and if the entry is used to access memory, the processor generates an abnormal paging mechanism (Paging Modes)

The paging mechanism provides a virtual memory environment in which virtual memory simulates a large linear address space through a small amount of physical memory and disk space. Under the paging mechanism, each segment is divided into many pages (usually one page is 4KB in size), either in physical memory or on disk. The operating system maintains a page directory and a set of page tables to track these pages. When a process attempts to access an address in a linear address space, the processor maps the linear address into a physical address through the page directory and the page table, and then operates (read or write). If the page being accessed is not in the current physical memory, the processor reads the missing page from the disk into physical memory and then executes the operation.

The information that the processor uses to map the linear address to the physical address and the information that produces the missing page exception are both in the page directory and in the page table, in memory.

To reduce the bus cycle used for address translation, the most recently visited page directories and page table entries are cached in a device called the transform fallback buffer (translation lookaside buffers, tlbs). TLBs can satisfy most requests to read the current Page directory and page table without consuming bus cycles. Additional bus cycles are required only if the page table entry you are accessing is not in tlbs.

Segments and pagination have essentially different pagination using fixed-size pages with fixed dimensions. The data structure of a process can be partially in memory, the size of each segment in the disk segment is not fixed, and it is related to the sum of the code that it holds. If only fragmentation is used as the only form of address translation, the data structure of a process must be all in physical memory

If the paging mechanism is not used, then the linear address is the physical address.

page tables and page catalogs
When the paging mechanism is started, the information that the processor uses for linear address-to-physical address translation is contained in 4 data structures in the page directory, an array of 32-bit page directory entries. It is placed on a 4KB page, and the page directory contains a maximum of 1024 page catalogs. A page table, an array of 32-bit page table entries. It is stored in a 4KB page, and the page table contains a maximum of 1024 page table entries. For 2MB and 4MB pages, the page table is not applicable. These pages are mapped directly from one or more page catalog entries. Page, a 4KB,2MB or 4MB flat address space. A page Catalog pointer table, an array of 4 64-bit items, each pointing to a page directory. This data structure is used only when physical address extensions are enabled.