IC front-end design and backend design process

Write your own understanding based on your personal knowledge. The front-end design (also known as logical design) and backend design (also known as physical design) do not have a uniform and strict boundary. the design related to the process is the backend design.

1. Specification formulation

Like the function list, the chip specifications are the design requirements raised by the customer to the chip design company (fabless, including the specific functional and performance requirements that the chip needs to meet.

 

2. Detailed Design

Based on the specifications required by the customer, fabless provides the design solution and specific implementation architecture, and divides the module functions.

 

3. HDL Encoding

The Hardware Description Language (VHDL, OpenGL, and industry companies generally use the latter) describes the module functions in code, that is to say, the actual hardware circuit functions are described through the HDL language to form the RTL (register transfer level) code.

 

4. Simulation Verification

Simulation Verification is to verify the correctness of the encoding design, and the testing standard is the specification set in the first step. Check whether the design meets all the requirements of the specifications accurately. The specification is the golden standard of design correctness or not. Any violation or non-compliance with the specification requirements requires re-modification of the design and encoding.

Design and Simulation Verification are iterative until the verification results show full compliance with specifications.

The VCs of the simulation verification tool Synopsys.

 

5. logical synthesis-Design Compiler

The simulation is verified and logic is integrated. The result of logical synthesis is to translate the designed implementation of the HDL code into a gate-level network table (netlist ). You need to set constraints for integration, that is, the criteria that you want the integrated circuit to meet in terms of area, timing, and other target parameters. Logical synthesis is based on a specific integrated library. In different databases, the area of the standard cell of the gate circuit is different in time series parameters. Therefore, the selected integrated database is different. The integrated circuit varies in time series and area.

In general, simulation verification is required again after the integration is completed (this is also called post-simulation, and the former is called pre-simulation)

Design Compiler of the logical synthesis tool Synopsys.

 

6. Sta

Static timing analysis (STA), static timing analysis, which is also part of the verification scope. It is mainly used to verify the circuit in time series and check whether the circuit has setup time) and hold time (Violation ). This is the basic knowledge of digital circuits. When these two sequence violations occur in a register, there is no way to correctly sample and output data, therefore, the register-based digital chip function will certainly be faulty.

The STA tool has the prime time of Synopsys.

 

7. Form Verification

This is also the scope of verification. It verifies the integrated network table in terms of function (STA is the time series. The commonly used method is the equivalence check method. Taking the functional verification-based HDL design as a reference, we will compare the comprehensive functions of the network table to see if they have the same functional equivalence. This is done to ensure that the circuit function described in the original HDL is not changed in the logical synthesis process.

The form verification tool has the formality of Synopsys.

 

The front-end design process is currently written here. In terms of design, the result of the front-end design is to obtain the gate-level network Table circuit of the chip.

 

 

8. DFT

Design for test, testability design. The chip usually comes with test circuits. The purpose of DFT is to consider future tests during design. A common method of DFT is to insert scan chains in the design and change non-scan units (such as registers) into scan units. I have a detailed introduction to DFT in some books. I 'd better understand it by referring to the picture.

DFT compiler of the DFT tool Synopsys

9. Layout Planning

Layout Planning is the macro unit module for storing chips. In general, the placement of various functional circuits is determined, such as IP module, ram, and I/O pins. Layout Planning directly affects the final chip area.

Astro of Synopsys

10. CTS

Clock Tree Synthesis: The Clock Tree is integrated. Simply put, it is the wiring of the clock. Because of the global command function of the digital chip, the clock signal distribution should be symmetric connected to each register unit, so that when the clock arrives at each register from the same clock source, minimum clock latency. This is also why the clock signal needs to be separately cabled.

CTS tool, Physical Compiler of Synopsys

11. Wiring

The cabling here refers to cabling of common signals, including cabling between various standard units (basic logical door circuits. For example, the 0.13um process we usually hear, or the 90nm process, is actually the minimum width that metal wiring can achieve here. In the microscopic view, it is the channel length of the mos tube.

Astro of the Synopsys Tool

12. Parasitic Parameter Extraction

Due to the resistance of the wire itself and mutual inductance between adjacent wires, the coupling capacitor will generate signal noise, crosstalk and reflection in the chip. These effects will cause signal integrity problems, resulting in signal voltage fluctuations and changes. If the signal is serious, it will lead to signal distortion errors. It is very important to analyze and verify the signal integrity by extracting parasitic parameters.

Star-rcxt of the Synopsys Tool

13. Physical verification of the layout

There are many verification items, including LVS (layout vs schematic) verification, to verify the function and timing of the physical layout that completes cabling. Simply put, it is the comparison and verification of the door-Level Circuit Diagram after the layout and logic synthesis; DRC (Design Rule Checking), design rule check, check whether the line spacing, line width, etc. meet the process requirements; ERC (electrical rule checking), electrical rule inspection, inspection of short circuit, open circuit and other electrical rule violations; and so on.

Hercules of the Synopsys Tool

The actual back-end process also includes circuit power analysis and DFM (manufacturing design) issues that arise as the manufacturing process continues to evolve.

The physical layout verification is completed, that is, the entire chip design phase. The following is the chip manufacturing process. The physical layout is handed over to the chip Foundry (known as foundry) in the format of gds ii to make the actual circuit on the wafer, and then encapsulate and test the chip.