IIC Bus Working principle (1)

Reprint: http://www.eefocus.com/article/08-07/48416s.html
Figure 11-1 shows a single-master IIC bus system with 3 slave machines from the MCU as a host through the IIC bus. This is the most commonly used, the most typical IIC bus connection mode.

On the physical structure, the IIC system consists of a serial data line SDA and a serial clock line SCL. The host addresses and transmits information to the slave according to a certain communication protocol. At the time of data transmission, the host initiates a data transfer, and the host transmits the data on the SDA line while transmitting the clock through the SCL line. The object and direction of information transmission and the beginning and termination of information transmission are determined by the host.
Each device has a unique address and can be a single-receiver device (e.g., an LCD driver) or a device that can be received or sent (for example, memory). The transmitter or receiver can operate in either main mode or slave mode, depending on whether the chip must initiate the transmission of the data or simply be addressed.
1. Validity of data on the bus

The IIC bus transmits data serially, starting at the highest bit of data byte, with each data bit having a clock pulse corresponding to the SCL. The logic level state must be stable on the data line during the high level of the clock line, the high level is data 1, and the low level is data 0. Only when the clock line is low, the level state on the data line is allowed to change, as shown in 11-2.

2. Signals on the bus
The IIC bus has four types of signals in the process of transmitting data, namely: start signal, stop signal, restart signal and answer signal .
Start signal (start): 11-3, when the SCL is high, SDA jumps from high level to low level, generating a start signal. When the bus is idle, for example, if no active device is using the bus (both SDA and SCL are high), the host establishes the communication by sending a start (start) signal.

Stop signal (STOP): 11-3, when the SCL is high, SDA jumps from a low level to a high level, resulting in a stop signal. The host ends the data communication by sending a stop signal.
Restart signal (repeated start): On the IIC bus, the host sends a start signal to start a communication, before the first send stop signal, the host by sending a restart signal, can be converted to the current slave communication mode , or switch to communication with another slave . 11-3, when the SCL is high, the SDA jumps from a high level to a low level, generating a restart signal, which is essentially a start signal.

Response Signal (A): The IC receiving the data sends a specific low-level pulse to the IC that sent the data after receiving the 8-bit data. each data byte is followed by a response signal indicating that the data has been received. The response signal appears in the 9th clock cycle, when the transmitter must release the data line on this clock bit, the receiving device pulls the SDA level to generate a response signal, the receiving device maintains the high level of SDA to produce a non-response signal (A (-)), 11-4 shows. Therefore, a full byte data transfer requires 9 clock pulses . If the slave as the receiving direction of the host to send a non-response signal, so that the host Party that the data transfer failure; If the host as the receiver, after sending a byte of data from the sender of the slave, send a non-response signal, the slave is considered the end of the data transfer, and release the SDA line. In either case, the data transfer is terminated, at which point the host either generates a stop signal to release the bus, or generates a restart signal to start a new communication. Start signal, restart signal and stop signal are generated by the main controller, the response signal is generated by the receiver, the bus with the IIC bus interface device is easy to detect these signals.

3. Data transfer format on the bus
In general, a standard IIC communication consists of four parts: Start signal, slave address transmission, data transmission, stop signal.
A start signal is sent by the host, which initiates an IIC communication, and then transmits the data on the bus after the host has addressed the slave. The IIC bus transmits each byte is 8 bits, first sends the data bit is the highest bit, each transmits one byte must follow an answer bit, each communication data byte number is not limited, after all data transfer ends, sends the stop signal by the host, ends the communication.

As shown in Figure 11-5, the clock line is low and the data transfer will stop. This can be used to force the bus to wait until the receiver is ready to receive the new data, and the receiver releases the clock line so that the data transfer continues normally when the sink receives a byte of data to do some other work and cannot immediately receive the next data. For example, when the receiver receives a byte of data from the host controller, generates an interrupt signal and interrupts processing, the interrupt is processed to receive the next byte of data, and the receiver will clamp the SCL low on interrupt processing until the SCL is released after the interrupt is processed.

4. IIC Bus Addressing conventions
In order to eliminate the address selection line of the main controller and the controller in the IIC bus system, to minimize the bus connection line, the IIC bus adopts a unique addressing convention, which specifies that the first byte after the start signal is the addressing byte, which is used to address the controlled device and specify the direction of data transmission.

In the IIC bus system, the addressing byte consists of the seven-bit address bit of the controller (which occupies the D7-D1 bit) and a direction bit (D0 bit).A direction bit of 0 indicates that the master writes data to the controller and 1 indicates that the master reads the data from the controller. Immediately after the host sends the start signal, the addressing byte is sent, and all devices on the bus compare the 7-bit address in the addressing byte to their own device address. If the two are the same, the device is considered to be addressed by the main controller and sends a response signal, the controller according to read, write bit determines whether itself as a transmitter or receiver.

When the master device acts as a controller, its 7-bit slave address is given in the IIC bus address register as a pure software address. The peripheral address of the non-microcontroller type is entirely given by the device type and pin level. In an IIC bus system, no two slave addresses are the same. The main controller should not transmit an address that is the same as its own from the address.

5. The process by which a host reads and writes 1 bytes of data to a slave machine
As shown in 11-6, when the host writes 1 bytes of data to the slave machine,The host first generates a start signal, followed by a slave address, which has 7 bits, followed by the 8th bit is the data direction bit (R/W), 0 means the host sends data (write), 1 indicates that the host receives data (read),At this time the host waits for the slave to answer the signal (A), when the host receives the answer signal, sends the address to be visited, continues to wait for the slave to answer the signal, when the host receives the reply signal, sends 1 bytes of data, continues waits for the slave to answer the signal, when the host receives the reply signal, produces the stop signal,

11-7, the host to read from the slave machine 1 bytes of data, the host first generates a start signal, and then immediately after sending a slave address, note that at this time the 8th bit of the address is 0, indicating that the command is written to the slave, when the host waits for the slave to answer the signal (A), when the host receives the response signal, Send the address to be accessed, continue to wait for the slave's answer signal, when the host receives the response signal, the host to change the communication mode (the host will be sent to receive, slave will be received into the send) so the host sends a restart signal, and then immediately send a slave address, note that at this time the address 8th bit 1, Indicates that the host is set to receive mode to start reading data, when the host waits for the slave to answer the signal, when the host receives a response signal, it can receive 1 bytes of data, when the reception is completed, the host sends a non-response signal, indicating that it is not receiving data, the host then produces a stop signal, end the transmission process.

(turn) IIC Bus working principle (1)