Implementation of ads7830 FPGA

General principles of PCB design Xilinx Learning Experience 1-pin constraints ads7830 FPGA Implementation

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The ads7830 is an 8-bit, 8-channel AD conversion chip of Ti, Which is configured and read through the I2C interface. The following is a program I have compiled using the OpenGL, which has been verified and is completely OK, the input clock is 125 MHz. After dividing the clock into 200 kHz, the I2C interface clock is adopted in kHz mode. To apply the clock to the upper-layer module, the inout type SDA is processed in the upper-layer module;

Module i2c_ads7830 # (parameter div_para = 625) (input CLK, input rst_n, input ad_req, input [] ad_channel, output Reg dout_valid, output Reg [] dout, // output Reg flag0, output Reg SCL, input sda_in, output Reg sda_out, output Reg en); localparam hard_addr = 8 'b1001 _ 0000; localparam i2c_idle = 4'd0, i2c_start = 4'd1, i2c_haddr = 4'd2, i2c_haddr_ack = 4'd3, i2c_cmd = 4'd4, i2c_1__ack = 4'd5, i2c_restart = 4'd6, i2c_wraddr = 4'd7, i2c_wraddr_ack = 4'd8, i2c_rdata = 4'd9, i2c_nack = 4'd10, i2c_stop = 4'd11;

Reg [] current_state; Reg [] ad_channel_buf; Reg [] databuf; Reg [] doutbuf;

Reg i2c_clk; Reg [9: 0] div_cnt; Reg [3: 0] i2c_cnt;

Reg start_ad; Reg ack_ad; Reg finish_ad; Reg finish_ad_reg0, finish_ad_reg1;

// [Email protected] (posedge CLK or negedge rst_n) // If (~ Rst_n) // flag0 <= 1' B0; // else if (finish_ad) // flag0 <= 1' B1; // Reg en; // Reg sda_reg; /// assign SDA = en? Sda_reg: 1' BZ;

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) i2c_clk <= 1 'b0; else if (div_cnt = DIV_PARA-1) i2c_clk <= ~ I2c_clk;

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) div_cnt <= 10 'd0; else if (div_cnt = DIV_PARA-1) div_cnt <= 10 'd0; else div_cnt <= div_cnt + 10' D1;

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) ad_channel_buf <= 3 'd0; else if (ad_req) ad_channel_buf <= ad_channel;

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) start_ad <= 1 'b0; else if (ad_req) start_ad <= 1 'b1; else if (ack_ad) start_ad <= 1 'b0;

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) Begin finish_ad_reg0 <= 1 'b0; finish_ad_reg1 <= 1' B0; end else begin future <= finish_ad; finish_ad_reg1 <= finish_ad_reg0; End

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) dout_valid <= 1 'b0; else if (finish_ad_reg0 &! Finish_ad_reg1) dout_valid <= 1 'b1; else dout_valid <= 1' B0;

[Email protected] (posedge CLK or negedge rst_n) if (~ Rst_n) dout <= 8'd0; else if (dout_valid) dout <= doutbuf;

[Email protected] (posedge i2c_clk or negedge rst_n) if (~ Rst_n) ack_ad <= 1 'b0; else if (start_ad) ack_ad <= 1 'b1; else ack_ad <= 1 'b0; [email protected] (posedge i2c_clk or negedge rst_n) if (~ Rst_n) finish_ad <= 1 'b0; else if (current_state = i2c_stop) finish_ad <= 1 'b1; else finish_ad <= 1 'b0; [email protected] (posedge i2c_clk or negedge rst_n) if (~ Rst_n) i2c_cnt <= 4'd0; else
Case (current_state) i2c_haddr, i2c_cmd, cursor, i2c_rdata: Begin if (i2c_cnt = 4'd15) i2c_cnt <= 4'd0; else i2c_cnt <= i2c_cnt + 4'd1; end i2c_start, begin, i2c_1__ack, lead, i2c_nack, i2c_stop: Begin if (i2c_cnt = 4 'd1) i2c_cnt <= 4 'd0; else i2c_cnt <= i2c_cnt + 4' d1; end i2c_restart: Begin if (i2c_cnt = 4 'd2) i2c_cnt <= 4'd0; else i2c_cnt <= i2c_cnt + 4'd1; end default: i2c_cnt <= 4'd0; endcase

[Email protected] (posedge i2c_clk or negedge rst_n) if (~ Rst_n) current_state <= i2c_idle; else case (current_state) i2c_idle: Begin if (start_ad) current_state <= i2c_start; end i2c_start: Begin if (i2c_cnt = 4'd1) current_state <= i2c_haddr; end i2c_haddr: Begin if (i2c_cnt = 4 'd15) current_state <= i2c_haddr_ack; end i2c_haddr_ack: Begin if (SCL &&! Sda_in) current_state <= i2c_cmd; else if (SCL & sda_in) current_state <= i2c_idle; // If (SCL) // current_state <= i2c_cmd; end i2c_cmd: begin if (i2c_cnt = 4 'd15) current_state <= i2c_1__ack; end i2c_1__ack: Begin if (SCL &&! Sda_in) current_state <= i2c_restart; else if (SCL & sda_in) current_state <= i2c_idle; // If (SCL) // current_state <= i2c_restart; end i2c_restart: begin if (i2c_cnt = 4 'd2) current_state <= i2c_wraddr; end i2c_wraddr: Begin if (i2c_cnt = 4 'd15) current_state <= i2c_wdrrad_ack; end state: begin if (SCL &&! Sda_in) current_state <= i2c_rdata; else if (SCL & sda_in) current_state <= i2c_idle; // If (SCL) // current_state <= i2c_rdata; end i2c_rdata: begin if (i2c_cnt = 4 'd15) current_state <= i2c_nack; end i2c_nack: Begin if (i2c_cnt = 4'd1) current_state <= i2c_stop; end i2c_stop: begin if (i2c_cnt = 4 'd1) current_state <= i2c_idle; end default: current_state <= i2c_idle; endcase [email protected] (posedge I2C _ CLK or negedge rst_n) if (~ Rst_n) Begin SCL <= 1 'b0; en <= 1 'b0; sda_out <= 1 'b0; databuf <= 8 'd0; doutbuf <= 8 'd0; end else case (current_state) i2c_idle: Begin SCL <= 1 'b1; sda_out <= 1 'b1; en <= 1 'b1; end i2c_start: begin if (i2c_cnt = 4 'd0) SCL in SCL <= 1 'b1; sda_out <= 1 'b0; end else SCL <= 1 'b0; databuf <= hard_addr; end i2c_haddr: Begin SCL <= ~ SCL; If (! SCL) Begin sda_out <= databuf [7]; databuf <= {databuf [6:0], 1 'b0}; end i2c_haddr_ack: Begin en <= 1 'b0; SCL <= ~ SCL; databuf <= {1 'b1, ad_channel_buf, 4' b0100}; end i2c_cmd: Begin en <= 1 'b1; SCL <= ~ SCL; If (! SCL) Begin sda_out <= databuf [7]; databuf <= {databuf [6:0], 1 'b0}; end i2c_1__ack: Begin en <= 1 'b0; SCL <= ~ SCL; databuf <= hard_addr + 1 'b1; end i2c_restart: Begin en <= 1 'b1; If (i2c_cnt = 4 'd0) Begin SCL <= 1 'b1; sda_out <= 1 'b1; end else if (i2c_cnt = 4'd1) Begin sda_out <= 1' B0; SCL <= 1' B1; end else SCL <= 1' B0; databuf <= hard_addr + 1' B1; end i2c_wraddr: Begin SCL <= ~ SCL; If (! SCL) Begin sda_out <= databuf [7]; databuf <= {databuf [6:0], 1 'b0}; end i2c_wraddr_ack: Begin en <= 1 'b0; SCL <= ~ SCL; end i2c_rdata: Begin en <= 1 'b0; SCL <= ~ SCL; If (! SCL) doutbuf <= {doutbuf [6:0], sda_in}; end i2c_nack: Begin en <= 1' B0; SCL <= ~ Check; end i2c_stop: Begin en <= 1 'b1; check <= 1 'b1; If (i2c_cnt = 4 'd0) sda_out <= 1 'b0; else sda_out <= 1 'b1; end default:; endcase

Endmodule

Implementation of ads7830 FPGA