Implementation of dsp_builder-based algorithms on FPGA

I. Summary

Combined with dsp_builder, Matlab, Modelsim, and Quartus II SoftwareAlgorithmFPGA implementation.

 

Ii. Experimental Platform

Hardware Platform: diy_de2

Software Platform: Quartus ii9.0 + Modelsim-Altera 6.4a (Quartus II 9.0) + dsp_builder9.0 + MATLAB 2010b

 

3. Prepare the software platform 1. Software matching

According to the official documents of Altera, you can see the version matching information of Quartus II, Modelsim, dsp_builder, and Matlab. 1.

Http://www.altera.com/support/ip/dsp/ips-dsp-version.html

Figure 1 software version matching

Generally, the Quartus II, Modelsim, and dsp_builder versions must match, while the MATLAB version is better than the specified version. However, this may cause some modules to be unavailable.

2. Software Installation

For instructions on how to install and crack dsp_builder, refer to the steps of "qingbreeze and moon ".Article, The link is as follows:

DSP Builder Installation Guide (in 9.1 as an example)

Note:

The MATLAB version of dsp_builder9.0 should be 2007b, while my version is 2010b. Although it is compatible, there are still some problems, such as some components of the advanced library cannot be displayed, as shown in figure 2. The best solution is to make the version fully match according to the suggestions.

Figure 2 some functions are unavailable

 

 4. Routine

Describes how to use dsp_builder through a sine wave routine. See the routine in Chapter 3rd of "EDA technology and VHDL" (9th) by Pan song.

1. Establish a simulation model of the simulation system.

Create a new simulation in MATLAB, as shown in figure 3.

Figure 3 simulation of the Simulation Model

2. Simulation of the simulation model (system-level, algorithm-level)

After setting the parameters, run the simulation. Double-click scope to view the simulation waveform, as shown in figure 4.

Figure 4 simulation of the simulation waveform in the chain

3. Use signalcompiler

After the simulation and verification are completed in Simulink, the design needs to be transferred to the hardware for implementation. This is the most critical step in the DSP Builder design. Based on this, we can obtain the FPGA-specific VHDL RTLCode.5.

Figure 5 signalcompiler

4. Use Modelsim for RTL-level simulation

This step is to simulate and verify the VHDL File converted from the. MDL file, which can be achieved by adding the testbench component. 6.

Figure 6 testbench

In addition, if you select the launch GUI, you can directly start Modelsim for simulation. If you do not select it, you can use TCL --> execute macro under the Tools menu of Modelsim... search for the sinwave_add.tcl file in the project folder for simulation.

5. Use Quartus II for timing simulation

The previous step is functional simulation, that is, the previous simulation in ModelSim. This is to further verify whether the timing simulation is correct, that is, the post-simulation. In this step, you need to describe the following points:

(1) The software prior to us II 9.1 comes with a simulation component, and later the software does not include this component.

(2) You can use Modelsim to simulate and verify the timing simulation.

6. FPGA Verification

Download the design to FPGA for verification. Use an oscilloscope to verify whether the waveform is correct.

 

V. Summary

For details about how to use each part of the above process, refer to the official documents of dsp_builder of Altera.

Introduction of dsp_builder: http://www.altera.com.cn/literature/hb/dspb/hb_dspb_intro.pdf

The basic database of dsp_builder: http://www.altera.com.cn/literature/hb/dspb/hb_dspb_std.pdf

Advanced database of dsp_builder: http://www.altera.com.cn/literature/hb/dspb/hb_dspb_adv.pdf