Implementation of FPGA three-state bus

In FPGA code design, remember to have a "principle". For three-state ports, try to use three-state ports in the top-layer modules instead of internal sub-modules. Otherwise, there will be a series of problems, I have always followed this principle to design the code. The figure shows a little curious. in the computer, most modules mounted on the bus are in three states, as a result, each of the three-state sub-modules connects to the outside through a top layer, FPGA, which uses hardware interconnection, should also have such capabilities. Therefore, the code used to implement the three-state bus in segments is written using Tilde. Compile with quartus9.1, observe the generated RTL circuit, and verify the idea.

First, design sub-modules with three-state ports ., The Code is as follows:

Module tricompoment1 (
CLK,
Iodata,
Odata,
Outen
);
Input CLK;
Input outen;
Output [7:0] odata;
Inout [7: 0] iodata;
Reg [7:0] data1, odata;
Assign iodata = (outen )? Data1: 8 'hzz;
Always @ (posedge CLK)
Begin
Data1 <= data1 + 8'd1;
Odata <= iodata;
End
Endmodule
At the top layer, multiple modules with three-state ports are connected, making the FPGA pins similar to the three-state bus.

Module tribus (
CLK,
Iodata,
Odata1,
Odata2
);
Input CLK;
Inout [7: 0] iodata;
Output [7:0] odata1, odata2;
Wire [7:0] iodata;
Reg outen1, outen2;
Tricompoment1 tricomp1 (
. CLK (CLK ),
. Iodata (iodata ),
. Odata (odata1 ),
. Outen (outen1)
);
Tricompoment1 tricomp2 (
. CLK (CLK ),
. Iodata (iodata ),
. Odata (odata2 ),
. Outen (outen2)
);
Always @ (posedge CLK)
Begin
Outen1 <= ~ Outen1;
Outen2 <= outen1;
End
Endmodule
The final RTL circuit structure

Module Internal Structure

In this way, the iodata pin becomes part of the three-state bus. I am a newbie. What's wrong? I hope you will criticize and correct me ~