Implementation of LVDS differential high-speed transmission in FPGA

Address: http://www.cnblogs.com/Jerome_Lee/archive/2010/04/19/1715457.html

 

 

Low-voltage differential transmission is based on low volt-AGC differential signaling, high-speed signal transmission from a circuit board system to fast data transmission between different circuit systems can be achieved using low-voltage differential transmission technology, and its application is becoming more and more important. Low-voltage differential signals have a high noise suppression function relative to single-end transmission, and their low voltage swing allows differential lines to have a high data transmission rate, low Power Consumption and lower electromagnetic radiation.

LVDS: low voltage differential signaling, low voltage differential signal.
The transmission speed of LVDS is generally 155 Mbps (about 77 MHz) or higher.
LVDS is a low-swing differential signal technology that enables signal transmission at several hundred Mbps on a differential PCB cable pair or balance cable, its low-voltage amplitude and Low-current drive output achieve low noise and low power consumption.

Differential signal noise resistance
It can be seen from the differential signal transmission line that, if the line is in ideal conditions and there is no interference,
On the sending side, the image can be understood:
In = in +-in-
On the receiving side, it can be understood:
In +-in-= out
Therefore:
Out = in
In actual line transmission, the line is subject to interference and appears on the differential line at the same time,
On the sending side, it is still:
In = in +-in-
The line transmission interference also exists in the difference pair. If the interference is Q, then the receiver will:
(In ++ q)-(In-+ q) = in +-in-= out
Therefore:
Out = in

The noise is stopped. The above can visually understand the ability of the differential method to stop noise.

 

XilinxUse of company difference primitives

(Primitive, whose English name is primitive, is the name of a series of common modules developed by Xilinx for its device features. Users can regard it as a library function provided by Xilinx for users, similar to the keyword "cout" in C ++, it is the basic component in the chip and represents the actual hardware logical units in FPGA, such as Lut, D Trigger, Ram, etc, it is equivalent to the machine language in the software. During the implementation process, all the design units must be translated into the basic components of the target device. Otherwise, it cannot be implemented. The primitive can be directly used as an example in the design, which is the most directCodeThe input method is similar to the relationship between the Assembly Language and the C language .)

DifferenceI/OPort Components

1)Ibufds

The ibufds primitive is used to convert a differential input signal into a standard single-ended signal and can be added with optional latencies. In the ibufds primitive, the input signal is I and IB, and the input signal is master and the input signal is slave.
The ibufds logical truth table lists the values. "-*" indicates that the output value remains unchanged.

The following is an example code template for the ibufds primitive:

// Ibufds: Differential input buffer)
// Applicable chips: Virtex-II/II-Pro/4, Spartan-3/3E
// Xilinx HDL Database Wizard version, ise 9.1
Ibufds #(
. Diff_term ("false "),
// Differential terminal, only available in Virtex-4 chips, can be set to true/flase
. Iostandard ("default ")
// Specify the level standard of the input port. If you are not sure, you can set it to default.
) Ibufds_inst (
. O (O), // clock buffer output
. I (I), // The frontend input of the differential clock, which needs to be directly connected to the port of the top-layer Module
. IB (IB) // negative end input of the differential clock, which must be directly connected to the port of the top-layer Module
);
// End the ibufds module sample Process

Http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0229_197.html

 2)Obufds

Obufds converts a standard single-ended signal to a differential signal. The output port must correspond directly to the output signal of the top-level module, and the ibufds is a pair of reciprocal operations. The truth table of the obufds primitive is listed in the table.

The obufds primitive sample code template is as follows:

// Obufds: Differential output buffer)
// Applicable chips: Virtex-II/II-Pro/4, Spartan-3/3E
// Xilinx HDL Database Wizard version, ise 9.1
Obufds #(
. Iostandard ("default ")
// Indicates the level standard of the output port.
) Obufds_inst (
. O (O), // differential positive end output, directly connected to the top-layer module port
. Ob (OB), // differential negative end output, directly connected to the top-layer module port
. I (I) // buffer input
);
// End the sample process of the obufds Module

Http://www.xilinx.com/itp/xilinx5/data/docs/lib/lib0317_301.html

3)Iobufds

OpenGL instantiation Template

// Iobufds: Differential bi-directional Buffer

// Virtex-II/II-Pro/4/5, Spartan-3/3E/ 3A

// Xilinx HDL libraries guide, version 9.1i

Iobufds #(

. Ibuf_delay_value ("0 "),

// Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-

3E only)

. Ifd_delay_value ("Auto "),

// Specify the amount of added delay for input register, "Auto", "0"-"8"

Spartan-3E only)

. Iostandard ("default") // specify the I/O standard

) Iobufds_inst (

. O (O), // buffer output

. Io (IO), // diff_p inout (connect directly to top-level port)

. IOB (IOB), // diff_n inout (connect directly to top-level port)

. I (I), // buffer input

. T (t) // 3-State enable Input

);

// End of iobufds_inst instantiation

 

DifferenceClock component

1)Ibufgds

Xilinx device primitives related to global clock resources are commonly used: ibufg, ibufgds, bufg, bufgp, bufgce, bufgmux, bufgdll, and DCM, as shown in 1.

Ibufgds is a differential form of ibufg. When a signal is input from a pair of differential global clock pins, ibufgds must be used as the global clock input buffer. Ibufg supports I/O standards in various formats such as blvds, LDT, lvdsext, LVDS, lvpecl, and ulvds.

Http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0231_199.html

OpenGL instantiation Template

Ibufgds instanece_name (. O (user_o ),

. I (user_ I ),

. IB (user_ib ));

References:

1) high-speed communication application research based on LVDS and FPGA, Han dang Qun, Tang conscription, Zhang Qingling

Http://www.eccn.com/xsj07/xsj080231.asp

2) Introduction to LVDS Principles and Applications

Http://www.ent.eetchina.com/ART_8800472639_2700004_TA_5d4d019d.HTM

3) LVDS User Manual of semiconductor USA

Http://www.ent.eetchina.com/ART_8800562170_2700004_TA_552cca6f.HTM

 

How does Xilinx FPGA use LVDS?

Http://www.61eda.com/Services/help/Xilinx/200803/1225.html

 

No matter whether you use hdflow or schematic flow, you can use LVDS by using differential buffers such as ibufds and obufds.

To locate the pin position and use pace, select lvds33 or lvds25 in Io standard, and select a version with DCI. When setting the port, note that the pin name in Datasheet is divided into P/N, which also corresponds to P in the buffer and N in the buffer. Note that the same bank can only have one voltage standard.

 

If you use the FPGA editor to observe the layout and wiring, you will find that the FPGA editor does not have the ibufds component, and the buffer is hidden in iob. click in the pin graph block, we can see that there is a buffer in it, which plays the role of ibufds.