First, let's clarify our programming steps.
(1) power up the program within 4 K of boot. s in nand_flash. This 4 K will be automatically copied to the SRAM (in-chip RAM) for execution.
(2) We need to use this 4 K program to copy the program after 4 K in NAND Flash (of course, copy the program to the base address of SDRAM at 0x30000000) and continue the execution (main. O part of the program ). The initialization of SDRAM and the disabling of watchdog have been used in the previous experiment. Let's take a look at the initialization and use of NAND Flash.
Check the space layout of the S3C2440. View the manual Figure 5-1. s3c2440a memory map after reset.
There are 8 banks-total 8 memory bankssix memory banks for Rom, SRAM, etc. remaining two memory banks for Rom, SRAM, SDRAM, etc.
Each bank has MB space. When you access bankx, the corresponding address range is 128 * n to 128*(1 + n) tq2440. The 64 m NAND Flash and 64 m sdromnand Flash do not correspond to any bank, it is accessed through several sets of registers. After power-on, 4 k Data starting with NAND Flash is automatically copied to a ram in the chip called steppingstone. Steppingstore's ing address is 0, and the above 4 K completes initialization; SDRAM uses bank6 and starts from 0x30000000
In this experiment, we will use the bank6 tutorial of SDRAM. Objective:
(1) Principle and working process of MEM Controller
(2) Use of bank
(3) read/write control of NAND Flash
(4) Start code Process Analysis
In actual programming, uboot and VIVI are both excellent reference source code. Here I refer to Vivi code.
Vivi has been uploaded to Sina share: http://ishare.iask.sina.com.cn/f/11353581.html
Introduction to the startup principle on datasheet:
Bank0: The data bus of bank0 (ngcs0) shocould be configured with a width as one of 16-bit and 32-bit ones. because thebank0 works as the booting ROM Bank (Map To 0x0000_0000), the bus width of bank0 shocould be determinedbefore the first ROM Access, which will depend on the logic level of Om [1:0] At reset.
The following is a summary of the operations on the NAND flash controller.
The configuration process of the nandflash read/write operation register is as follows:
The configuration process of the nandflash read/write operation register is as follows:
1. Initialization
(1) nfcont = (1 <0) // enable NAND Flash Controller
(2) nfcont | = (1 <0) // chip disable
2. Reset
(1) nfcont & = ~ (1 <1) // chip enable
(2) nfcmd = 0xff; // reset command
(3) While (! (Nfstat & busy) waiting for NAND flashmemory ready to operate
3. Read Functions
(1) nfcont & = ~ (1 <1) // chip enable
(2) nfstat | = (1 <2) // nand_clear_rb, rnbtransition is detected
(3) nfcmd = 0; // read0, read the upper half
(4) // write address
Nfaddr = I & 0xff;
Nfaddr = (I> 9) & 0xff;
Nfaddr = (I> 17) & 0xff;
Nfaddr = (I> 25) & 0xff;
(5) While (! (Nfstat & (1 <0); // nand_detect_rb, waiting for nandflash memory ready to operate
(6) * Buf = (nfdata & 0xff); // read data line
(7) nfcont | = (1 <1) // chip disable
Source code of the NAND Flash initialization read operation:
1/* reset the NAND flash before the first practical NAND Flash */
2 void nand_flash_reset ()
3 {
4 nand_chip_enable;
5 nfcmd = 0xff; // reset command
6 wait_idle ();
7}
8
9/* initialize NAND Flash */
10 void nand_flash_init ()
11 {
12 // Vivi init
13 int I = 0;
14 nfconf = (7 <12) | (7 <8) | (7 <4) | (0 <0 ));
15 nfcont = (1 <4) | (0 <1) | (1 <0); // active low Ce Control
16 nfstat = (0x6); // rnb clear
17 nfcmd = 0xff; // reset command
18 For (I = 0; I <10; I ++)
19;
20 wait_idle ();
21 /*
22 //----------------------------------------------------------------
23 // Following is the copy Module
24 //----------------------------------------------------------------
25 nfcont | = 0x2; // @ flash memory chip disable
26 //----------------------------------------------------------------
27 @ flash memory chip disable
28 @ get read to call C functions (for nand_read ())
29 @ copy Vivi to ram
30 LDR r0, = vivi_ram_base
31 mov R1, #0x0
32 mov R2, #0x20000
33 BL nand_read_ll
34 //---------------------------------------------------------------
35 */
36 /*
37 nfcont = (1 <0 );
38 nand_chip_disable;
39 nand_flash_reset ();
40 */
41}
42
43 # define busy 1
44 inline void wait_idle (void)
45 {
46 While (! (Nfstat & busy ));
47 nfstat | = busy;
48}
49
50 # define nand_sector_size 512
51 # define nand_block_mask (nand_sector_size-1)
52
53/* low level nand read function */
54 int nand_flash_read (unsigned char * Buf, unsigned long start_addr, int size)
55 {
56 int I, J;
57
58 If (start_addr & nand_block_mask) | (size & nand_block_mask )){
59 return-1;/* invalid alignment */
60}
61
62 nand_chip_enable;
63
64 for (I = start_addr; I <(start_addr + size );){
65/* debug */
66 (* (volatile unsigned long *) 0x56000010) = 0x00015400;
67 (* (volatile unsigned long *) 0x56000014) = 0x00000000;
68/* debug */
69/* read0 */
70 nand_clear_rb;
71 nfcmd = 0;
72
73/* write address */
74 nfaddr = I & 0xff;
75 nfaddr = (I> 9) & 0xff;
76 nfaddr = (I> 17) & 0xff;
77 nfaddr = (I> 25) & 0xff;
78
79 nand_detect_rb;
80
81 For (j = 0; j <nand_sector_size; j ++, I ++ ){
82 * Buf = (nfdata & 0xff );
83 Buf ++;
84}
85/* debug */
86 if (I> = 512)
87 {
88 for (j = 0; j <2048; j ++)
89;
90 (* (volatile unsigned long *) 0x56000014) & = (1 <5) & (1 <6 );
91 for (j = 0; j <2048; j ++)
92;
93}
94/* debug */
95}
96 nand_chip_disable;
97 return 0;
98}
Start the assembly code executed in SRAM:
1 @----------------------------------------------------
2 @ boot. s
3 @ yeven @ 2010.20.28
4 @----------------------------------------------------
5. Text
6. Global _ start
7 _ start:
8 LDR sp, = 4096
9 BL disable_wd @ disable the Watchdog
10 BL memsetup @ initialize SDRAM
11 BL nand_flash_init @ initialize NAND Flash
12
13 @ The following calls nand_flash_read. It requires three parameters: target address, source address, and data length.
14 LDR r0, = 0x30000000 @ new starting position of SDRAM
15 mov R1, #4096 @ main. O offset in NAND Flash, that is, the starting position of the data
16 mov R2, #1024 @ copy Length
17 BL nand_flash_read @ call the copy function in vivi code
18
19
20 BL led_on_s
21 ldr pc, = set_sp @: Set the stack and go to main. O for execution.
22 set_sp:
23 LDR sp, = 0x34000000 @ set the top pointer of the stack
24 ldr lr, = halt_loop @ set the return address of the Main Function
25 ldr pc, = Main @ executes the main function
26
27 halt_loop:
28 B halt_loop
29
30 led_on_s:
31 LDR r0, = 0x56000010.
32 mov R1, #0x00000400
33 STR R1, [R0]
34 LDR r0, = 0x56000014
35 mov R1, #0x00000000.
36 STR R1, [R0]
The main function executes the code, which will be executed in the sdram-0x30000000. He just keeps flashing:
1 /*
Mem-con.c yeven @ 2010.10.27
3 * learn to use the SDRAM, control the memory and Memory Map
4 * the main program locate at boot. s
5 * We just light the four LEDs to test the result.
6 */
7
8 // register for the LED
9 # define gpbcon (* (volatile unsigned long *) 0x56000010)
10 # define gpbdat (* (volatile unsigned long *) 0x56000014)
11
12 // led-data register value (GPB5-GPB8)
13 # define led0_on (1 <(5*2 ))
14 # define ledbench on (1 <(6*2 ))
15 # define led2_on (1 <(7*2 ))
16 # define led3_on (1 <(8*2 ))
17 # define gpb_on (N )(~ (1 <n ))
18 # define gpb_off (N) (1 <n)
19
20 void delayms (unsigned int N)
21 {
22 int I = 0;
23 For (I = 0; I <10240 * n; I ++)
24;
25}
26
27 int main ()
28 {
29 gpbcon | = (led0_on | led1_on | led2_on | led3_on); // led0-4
30 While (1)
31 {
32 gpbdat | = (gpb_on (5) | gpb_on (6) | gpb_on (7) | gpb_on (8 ));
33 delayms (1 );
34 gpbdat & = (gpb_off (5) & gpb_off (6) & gpb_off (7) & gpb_off (8 ));
35 delayms (1 );
36}
37
38 return 0;
39}
40
Compiled makfile and gnu ld files:
Sections
{
First 0x00000000: {boot. O init. O}
Second 0x30000000: At (4096) {nand-flash-con.o}
}
1 NAND-flash-Con: init2.c init. h nand-flash-con.c boot. s
2 arm-Linux-gcc-c-o boot. O boot. s
3 arm-Linux-gcc-c-o init. O init2.c # init. h
4 arm-Linux-gcc-c-o nand-flash-con.o nand-flash-con.c
5 arm-Linux-LD-tnand. LDS boot. O init. O nand-flash-con.o-O nand-flash-con-tmp.o
6 arm-Linux-objcopy-O Binary-s nand-flash-con-tmp.o NAND-flash-con
7 arm-Linux-objdump-D-B Binary-M arm NAND-flash-con> TTT. s
8 clean:
9 RM *. o
10 rm nand-flash-con
Implementation of NAND Flash (abstract, reference)
