Improve the real-time performance of uC/OS and Il with coprocessor

Improve the real-time performance of IJLC/OS n and Il with coprocessor

[Date: 2008-10-7]

Source: single-chip microcomputer and Embedded System Application Author: Tsinghua University Feng Zedong Shao Beibei

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Introduction
μC/OS-II supports a maximum of 63 tasks and multiple inter-process communication mechanisms such as semaphores, mailboxes, and message queues. At the same time, users can crop the functional modules in the kernel as needed. The Application of μC/OS-II to embedded systems is of great significance to improve product quality, shorten the development cycle and reduce the cost.
In order to ensure the real-time performance of the system, the μC/OS-II adopts the look-up table strategy, so that the task with the highest priority can run immediately once it enters the ready state. This lookup algorithm is independent of the number of tasks in the application system. The execution time is a fixed value, which ensures the hard real-time performance of the system. In the real-time kernel of μC/OS-II, the only function affected by the number of tasks is the clock cycle, and the interrupt service subroutine of the clock cycle needs to traverse all the tasks using the delay function, therefore, the execution time is related to the number of tasks, which is not a fixed value. In addition, the frequency of the clock cycle can not be too high, otherwise it will be due to frequent loading of Interrupt Service subprograms, resulting in increased CPU load, affecting the real-time μC/OS-II.
The 16-bit HCS12X ("S12X" for short) microcontroller of Freescale introduces a coprocessor named "XGATE ". Unlike the floating-point coprocessor in the general sense, this coprocessor is mainly used to handle interruptions. If a co-processor is used to handle the interruption of the μC/OS-II clock cycle, the master CPU does not need to frequently load the interrupt service subroutine to ensure that all function execution times of the μC/OS-II kernel are fixed. In this way, the real-time performance of μC/OS-II is guaranteed, and it can improve the accuracy of the application system timing by improving the frequency of clock interruption.

1. coprocessor in Single Chip Microcomputer
The XGATE coprocessor in the HCS12X series single-chip microcomputer is a processor with a simplified instruction set structure. Its clock frequency is twice that of the S12X master CPU. When initializing the system, the main CPU can decide to use or disable XGATE. If used, the XGATE runs independently after initialization and exchanges data with the CPU through the dual-port RAM. If necessary, an interrupt request is sent to the master CPU.
After processing all the interrupts, XGATE enters the sleep state and stops running until the next interruption occurs. XGATE is suitable for responding to high loading frequency interruptions or I/O interruptions without a communication buffer, such as SCI sending or receiving interruption and PWM output interruption. However, the benefits of using a coprocessor to handle interruptions with sending and receiving buffers (such as CAN interrupt and USB interrupt) are not obvious.
μC/OS-II clock cycle interrupt is a frequent interrupt, so it is suitable to use XGATE to respond. The following describes how to use the XGATE coprocessor to respond to the clock cycle interruption of μC/0S-II.

2 Use xgate to realize the clock cycle of μC/OS-II
Real-Time Interrupt (RRTI) can be used to Interrupt the clock cycle of μC/0S-11. Of course, you can also use the counter in the timer to generate the clock cycle. The principle is the same and the method is similar. When XGATE is used to respond to the failure of the RTCs, the division of work between the XGATE coprocessor and the primary CPU is shown in table 1.

XGATE is responsible for responding to the failure of the RTCs, implementing the clock cycle, and counting the task delay. After the task delay is completed, it notifies the CPU to schedule the task. In addition, XGATE is used to respond to other interruptions and notify the CPU when task scheduling is required. The master CPU is only responsible for running tasks (including system tasks) and task scheduling. The interrupt service subroutine is loaded only when task scheduling is required. The following describes how to use XGATE to set the clock cycle.
2.1 give control of the failure of the RTI instance to the xgate instance
In order to handle the RTCs interruption by XGATE, you must set the interrupt control register corresponding to the RTCs interruption in the S12X microcontroller during system initialization. The interrupt control register is composed of the following:

In the S12X microcontroller, each I/O interrupt corresponds to an interrupt control register. The interrupt control register controls whether the corresponding interrupt is returned by the S12X CPU or the XGATE, and the priority of the interrupt.
In the interrupt control register, when the RQST bit is 1, The XGATE responds to the interrupt; when the RQST bit is 0, the S12X CPU responds to the interrupt. In order to use XGATE to respond to the failure of the fault, the RQST position of the interrupt control register corresponding to the failure of the fault must be 1. PRIOLVL [2: 0] stores the priority of the corresponding interrupt. The larger the value, the higher the priority of the corresponding interrupt. If all three digits are 0, the corresponding interrupt will be disabled.
You can call the ROUTE_INTERRUPT function provided by the compiler to set the interrupt control register. The parameter required by this function is the offset of the interrupt vector corresponding to the base address (0xFF00) of the interrupt vector and the value of the interrupt control register. The code for setting the RFM interrupt control register is as follows:
RUUTE_INTERRUPT (0xF0, 0x81 );
0xF0 is the offset of the interrupt vector relative to the base address of the interrupt vector table, and 0x81 is the value of the interrupt control register to be set.
2.2 data sharing between xgate and s12x CPU
XGATE Implementation of μC/OS-II clock cycle and S12X CPU to achieve task scheduling, all need to access the system's task control block linked list related variables, therefore, these variables must be declared as shared variables of XGATE and S12X CPU. The "volatile" type declaration must be added to the declaration of shared variables, and the "# pragma" pre-processing command should be used to put them in the shared memory.

The S12 CPU program declares the following:

In the XGATE program, use extern to declare these variables. The specific statement is as follows:

2.3 pointer variable transformation between xgate and s12x CPU
Because the XGATE memory space address is different from the memory space address of the S12X CPU, there will be problems when sharing pointer variables. The difference between the CPU memory space and the XGATE memory space is 1.

As shown in figure 1, in the addressing space of the S12X CPU, 0x1000 ~ 0x3FFF is the RAM space. For XGATE, the address range of the RAM space is Ox8000 ~ 0 xFFFF. If the XGATE program directly uses the CPU pointer variable, the XGATE access address space may be 0x1000 ~ 0x3FFF, The XGATE is Flash in this region, and thus an error occurs. To correctly share pointer variables, you need to change the pointer variables when using the S12x CPU pointer variables in XGATE. The Address Allocation of different MCU members in the S12X series may be different. Take MC9S12XDT512 single-chip microcomputer as an example. There is a total of 8 KB non-Paging RAM in it, which can be set
XGATE shared memory. The address of these 8 kb ram in the S12X CPU is 0x2000 ~ 0x3FFF; the address in XGATE is 0xE000 ~ 0 xFFFF, the address deviation is 0xC000. Therefore, when XGATE uses the pointer variable of the S12X CPU, it can be used normally in the XGATE program by adding the value of the pointer variable to the offset 0xC000.
The code for converting pointer variables in the XGATE program is as follows:

There are eight registers in the XGATE coprocessor. the compiler uses R1 to pass parameters. The R2 and R3 In the above program are the other two of the eight registers.
2.4 communication between xgate and s12x CPU
When XGATE is used to process the interruption of the RTC, the pointer transformation is completed first, and then all the tasks of the μC/OS-II are traversed to control the block linked list, and the delay counter minus 1 operation is performed on the tasks that require delay. If no task scheduling is required, XGATE returns to sleep state until the next interruption is returned. Only when the delay counter of a task is reduced to zero, the task enters the ready state and the S12X CPU is notified to switch the task only when the task is scheduled.
In the interrupt service subroutine of XGATE, the interrupt mark command SIF is used to send an interrupt request to the S12X CPU. This command sets the interrupt flag, and requests the S12X CPU to continue responding to this RTR interruption. The code for using the SIF command in the XGATE interrupt service subroutine is as follows (R5 is one of the eight registers of the XGATE coprocessor ):

The xgate completes the traversal task control block linked list and the operation of reducing the task delay counter by 1, and the Failure response to the task without task scheduling, the s12x CPU only needs to respond to the restart interruption that requires task scheduling, which greatly simplifies the interrupted service Subroutine:

In this way, the code to be executed by the interrupt service subroutine of the CPU is fixed, and the running time of each operation is also a fixed value, so the real-time performance of the μC/OS-II is guaranteed.
The procedure 2 of the s12x CPU and xgate is shown.

2.5 set an xgate vector table
In order to make the xgate respond to the interruption normally, you need to write the xgate RTI interrupt service subprogram address to the xgate interrupt vector table. The method of xgate interrupt vector table is similar to that of CPU interrupt vector, but the interrupt subprogram of xgate can be substituted into a parameter, which needs to be written into the interrupt vector table.
When the xgate interrupt vector table is determined and the address and parameter variable of the RTI interrupt service subprogram are written, the xgate interrupt service subprogram can be entered in response to the RTI interrupt.
The xgate interrupt vector table is written as follows:

Among them, ostcblist is the xgate in response to the interruption of the RTR parameters, here this parameter is the first address of the μC/OS-II task control block linked list; xgate_tableentry is a struct variable type customized by the compiler; xgate_vectortable [] is the xgate interrupt vector table. After the xgate interrupt vector table is written, the process of setting the μ c/OS-II clock cycle with xgate is completed.

3. Performance Testing and Analysis
In order to verify the effect of using coprocessor to deal with clock cycle interruption, the following tests are carried out: Using and not using XGATE to process the clock cycle interruption of μC/OS-II on the same-S12x microcontroller. In both cases, the same 10 tasks are created, and only the linked list traversal of the task control block and the delay counter minus 1 are performed in the clock cycle interrupt service subroutine, without task scheduling. In this way, a task in the μ C/OS-II is always in ready state and always running, and this always running task will output a square wave on an I/O port by means of cyclic counting. Compare the difference between two kinds of μC/OS-II output square wave cycles under the same bus clock and the same frequency clock cycle.
The purpose of the test is to observe the effect of the loading of the sub-Program of the interrupt service on the clock cycle of the μC/OS-II on the running tasks in the system. In order to compare with XGATE processing task control block linked list traversal and delay counter minus 1, XGATE's μ C/OS-II is not used, the clock cycle interrupt service subroutine of the S12X CPU only retains the same operations as the XGATE. Without task scheduling, you can also observe the square waves output by running tasks in the system.
In the μC/OS-II of the xgate that is not used, the interrupt service subroutine code of the RTI interrupt of the S12X CPU is as follows:

The preceding S12X CPU interrupt service subprograms have a total of 220 commands and need to run for 538 cycles. 16 MHz bus clock and 16 kHz μC/OS-II clock cycle were used in the test. It can be estimated that the running time of each interrupt service subprogram in the S12X CPU is 33.6 μs, which is about 62.5 of the clock cycle of 53% μs, that is, the S12X CPU needs to respond to the clock cycle interruption with more than half of the time, which is obviously not desirable.
When XGATE is used in μC/OS-II to handle clock cycle interruption, when task scheduling is not required, XGATE traverses the control block linked list of 10 tasks and executes the delay counter minus 1 operation, A total of 148 commands are required. Because XGATE is a processor of the RISC structure, the command execution time is usually 1 ~ Two cycles. Therefore, it takes 148 cycles to execute 218 commands. At a 32 MHz clock frequency, the execution time is about 7 μs, which is only 62.5 of the 11% μs clock cycle. This indicates that even if a clock is used as short as 62.5 μs
The usage of XGATE is not high.
Through the above test, we can see that by a single CPU running μC/OS-II, 16 kHz clock cycle causes the s12x CPU to frequently load interrupt service subroutines, occupying more than 50%, seriously affects the real-time running of tasks. Therefore, for a single CPU, the general use of the clock cycle frequency is not higher than 100Hz, at this time the timing accuracy is ± 10 MS, in order to avoid clock cycle interruption takes a lot of CPU running time.
When xgate is used to process the clock cycle of μC/OS-II, the 16 kHz clock cycle does not affect the running of the s12x CPU task, the clock cycle of this frequency makes the timing accuracy of μC/OS-II higher than ± 62. 5 μs. The coprocessor xgate is used to process the clock beat of μC/OS-II, so that the execution time of the main CPU is fixed, so the real-time operation of the task is ensured, and the real-time system is improved, high-frequency Clock beats also increase the timing accuracy.

4 Conclusion
In the μC/OS-II, the sub-Program of the interruption of the clock cycle needs to traverse the whole task control block linked list, the number of tasks in different applications is different, and the time spent in traversing the whole task control block linked list is different. The uncertainty brought about by clock cycle interruption is the only factor that affects the real-time performance of μC/OS-II. Using coprocessor to realize the clock cycle of μC/OS-II can solve this problem well.
If a coprocessor is used to respond to the clock cycle interruption of the μ c/OS-II, The traversal of the block linked list and the delay counter minus 1 operations are completed by the coprocessor. The main CPU enters the corresponding interrupt service subroutine only when task scheduling is required. Therefore, the duration for the main CPU to run the interrupt service subroutine is a fixed value. Because the running time of the main CPU is not occupied by the clock cycle interruption, it can improve the timing precision of μC/OS-II by using a very high frequency clock cycle.