In-depth analysis of nand flash memory

For many consumer audio and video products, NandFlash MemoryIt is a better storage solution than hard drive, which is particularly evident in low-capacity applications with a size not more than 4 GB. As people continue to pursue products with lower power consumption, lighter weight, and better performance,NandIt is proving very attractive.

The nand flash memory array is divided into a series of KB blocks, which are the smallest erasable entities in the NAND device. To erase a block, all bits are set to 1 (and all bytes are set to FFH ). It is necessary to program to change the erased bits from "1" to "0 ". The smallest programming entity is byte ). SomeNorFlash memory can simultaneously perform read/write operations (see figure 1 ). Although NAND cannot perform read/write operations at the same time, it can use a method called "shadowing" to achieve this at the system level. This method has been used on PCs for many years, that is, loading BIOS from low-speed Rom to high-speedRam.

Nand is highly efficient because there are no metal contacts in the NAND string. Size ratio of nand flash memory unitsNorThe reason for the small size (4f2: 10f2) is that each unit of nor requires an independent metal contact. Like a hard drive, Nand is based on slices (pages) and suitable for storing continuous data, slices, audios, or PC Data. Although you can achieve random access at the system level by ing data to Ram, this requires additional Ram storage space. In addition, like a hard disk, the NAND device has bad sectors and requires an error correction code (ECC) to maintain data integrity.

The smaller the storage unit area, the smaller the bare part area. In this case, Nand can provide a larger storage capacity for today's low-cost consumer market. Nand flash memory is used for almost all erasable memory cards. The NAND multiplexing interface provides a similar pin output for all the latest devices and density. This pin output allows design engineers to migrate from a smaller density to a larger density without having to change the hardware design of the circuit board.

Comparison between NAND and nor flash memory

Nand flash memory features fast write (programming) and erase operations, while nor features random access and write (programming) operations on bytes (see figure 2 ). Nor's random access capability supports direct Code Execution (xip), which is often required by embedded applications. The disadvantage of NAND is the slow speed of random access, and the disadvantage of nor is that it is restricted by the slow speed of reading and erasure. Nand is suitable for storing files. Nowadays, more and more processors have direct NAND interfaces and can directly import data from NAND (without nor.

The real benefit of NAND is fast programming and short erasure time. Nand supports continuous write operations with a speed greater than 5 Mbps. The block erasure time is as short as 2 ms, and the nor value is 750 ms. Obviously, Nand has absolute advantages in some aspects. However, it is not suitable for direct random access.

For 16-bit devices, the nor flash memory requires about 41 I/O pins, And the NAND device requires only 24 pins. The NAND device can reuse commands, addresses, and data bus to reduce the number of pins. One benefit of reusing interfaces is the ability to use the same hardware design and circuit board to support larger NAND devices. Since the general TSOP-1 package has been used for many years, this feature allows customers to transplant higher density NAND devices to the same circuit board. Another advantage of the NAND device is obviously its encapsulation option: NAND provides a thick film of 2 GB bare film or supports up to four stacked bare films, allows an 8 GB device to be stacked in the same TSOP-1 package. This enables a encapsulation and an interface to support high density in the future.

Figure 1 Comparison of Different flash memory units

Figure 2 the random access time of the nor flash memory is 0.12 ms, and the random access speed of the first byte of the nand flash memory is much slower.

Basic NAND operations

Taking the 2 gb nand device as an example, it consists of 2048 blocks, each of which has 64 pages (see figure 3 ).

Figure 3 2 gb nand flash memory contains 2,048 Blocks

Each page contains a 2048-byte data zone and a 64-byte free zone, with a total of 2,112 bytes. The free zone is usually used for ECC, wear leveling, and other software overhead functions, although it is physically no different from other pages. The NAND device has 8 or 16-bit interfaces. The master data is connected to the NANDMemory. In the 16-Bit mode, the command and address only use eight lower bits, while the 8-bit higher is only used in the data transmission cycle.

The time required to erase a block is about 2 ms. Once the data is loaded into the register, it takes about 300 μs to program a page. It takes about 25 μs to read a page, involving storage array access pages and loading the page into the 16,896-bit register.

In addition to the I/O bus, the NAND interface consists of six main control signals:

1. Chip enable (Ce #): If no CE signal is detected, the NAND device maintains the standby mode and does not respond to any control signals.

2. Write enable (we #): We # writes data, addresses, or commands into NAND.

3. Read enable (Re #): re # allows the output data buffer.

4. Command latch enable (CLE): When the CLE is high, the command is locked to the NAND command register in the rising edge of the we # signal.

5. Address latch enable (ALE): When ale is high, the address is locked to the NAND address register in the rising edge of the we # signal.

6. Ready/busy (ready/busy, R/B #): If the NAND device is busy, the R/B # signal will decrease. This signal is an open circuit with a drain pole and must use a pull-up resistor.

Each incoming/outgoing NAND Register uses a 16-bit or 8-bit interface. When programming, the data to be programmed enters the data register and is on the rising edge of the we # signal. Use special commands to randomly access or move data in registers for random access.

The data output in the data register is similar to the RE # signal. It outputs the existing data and adds it to the next address. We # And re # clock run extremely fast, reaching the 30ns level. When re # Or ce # is not low, the output buffer is in three states. This combination of Ce # And re # enables output buffers, allowing nand flash memory to share data bus with other types of memory such as nor, SRAM, and dram. This feature is sometimes called "chip enable don't care )". The original intention of this solution is to adapt to older NAND devices, which require ce # to be low throughout the cycle ).

Figure 4 when the input register receives the page programming (80 h) instruction, it will be reset to 1 s internally, so that the user can only input the data byte he wants to program in 0 bits.

Figure 5 Programming commands with random data input. The highlighted slice in the figure shows that this command only needs the address of 2 bytes following the data

All NAND operations start with a command cycle (table 1 ).

When a series of we # clock is output, you can implement a command cycle by setting the command on the I/O bit, driving ce # To lower and CLE to increase. Note: On the rising edge of the we # signal, commands, addresses, or data are locked to the NAND device. As shown in table 1, most commands occupy several address periods after the second instruction period. Note: The reset or read STATUS Command is an exception. If the device is busy, new commands should not be sent.

Taking the addressing scheme of the 2 gb nand device as an example, the first and second address cycles specify the column address, which specifies the start byte in the page (table 2 ).

Note: because the position of the last column is 2112, the address of the last position is 08 h (in the second byte) and 3fh (in the first byte ). Pa5: 0 specifies the page address in the block, and ba16: 6 specifies the address of the block. Although most programming and read operations require a complete 5-byte address, the random access to data on the page only uses the first and second bytes. The block erasure operation only requires three maximum bytes (the third, fourth, and fifth bytes) to select the block.

Figure 6 typical Storage Methods

Figure 7 page read cache Mode

In general, the basic operations of NAND include: reset (reset, FFH) operation, read ID (read ID, 00 h) operation, read status (read status, 70 h) operations, program operations, random data input (85 h) operations, and read operations.

Connect NAND to the processor

There are many benefits to choosing a processor or controller with built-in NAND interfaces. Without this option, it is possible to design a "glueless" interface between NAND and almost any processor. The main difference between NAND and nor flash memory is the reuse of address and data bus. This bus is used to specify commands, addresses, or data. The CLE signal specifies the instruction period, while the ale signal specifies the address period. Using these two control signals, You may select commands, addresses, or data periods. Connect ale to the fifth address bit of the processor, and connect CLE to the fourth address bit of the processor. You can simply change the output address of the processor and select any command, address, or data. This allows CLE and ale to be automatically set to low at the appropriate time.

To provide commands, the processor outputs the desired commands on the Data Bus and outputs the address 0010 H. to output any number of address cycles, the processor only needs to output the desired NAND address after the processor address is 0020h in sequence. Note that many processors can specify a number of time series parameters around the write signal of the processor, which is crucial to establishing a suitable time series. With this technology, you can directly access commands, addresses, and data from the processor without using any bonding logic.

Multi-layer Unit

Each unit of a multi-layer unit (MLC) is stored in two places, while the traditional SLC can only store one bit. MLC technology has significant density advantages. However, compared with SLC (table 3), MLC has lower speed or reliability. Therefore, SLC is used for most media cards and wireless applications, while MLC devices are usually used for consumer electronics and other low-cost products.

As described above, Nand requires ECC to ensure data integrity. Each page of the nand flash memory contains additional storage space, which is a 64-byte Free Zone (16 bytes for each 512-byte sector ). This area can store ECC code and other information such as wear rating or logical-to-physical block ing. ECC can be executed in hardware or software, but hardware execution has obvious performance advantages. During programming, the ECC unit calculates the error code correction code based on the data stored in the slice. The ECC code of the Data zone is then written to the separate idle zone. When data is read, the ECC code is also read. The reverse operation can be used to check whether the read data is correct.

ECC algorithms may be used to correct data errors. The number of errors that can be corrected depends on the intensity of the algorithm used. Including ECC in hardware or software provides powerful system-level solutions. The simplest hardware implementation scheme is to use a simple hamming code, but only one-bit error can be corrected. The Reed-Solomon Code provides more powerful error correction and is widely used by current controllers. In addition, BCH Code is increasingly popular because it is more efficient than the redsorot method.

Use software to perform block management for nand flash memory. The software is responsible for wear rating or logical to physical ing. The software also provides ECC codes if the processor does not contain ECC Hardware.

After programming or erasure, it is important to read the Status Register because it determines whether the program or erasure operation has been completed successfully. If the operation fails, mark the block as corrupt and unusable. Previously written data should be moved from the damaged block to the new (good) block. 2 gb nand specifications stipulate that it can have up to 40 Bad blocks, which are applicable to the device's life cycle (Rated Life of 0.1 million programming/erasure cycles. Some NAND devices with bad blocks can leave the factory, mainly because of their large bare area. Software managing devices Maps bad blocks and replaces them with good storage blocks.

The software scans the blocks to determine whether the blocks are good or bad by using the factory's tags. The first position of the Bad Block mark that is fixed in the idle zone (column address 2048 ). If the data on column address 2048 on pages 0 or 1 is "non-FF", the block should be marked as bad and mapped out to the system. The initialization software only needs to scan all blocks to determine which one is bad, and then create a bad block table for future reference.

Be careful not to erase the bad block tag, which is important. The plant tests NAND in a wide, moderate, and wide voltage range. Some blocks marked as bad by the factory may still work at a certain temperature or voltage, but may become ineffective in the future. If the bad block information is erased, it cannot be restored.

By Jim Coke

Chief Application Engineer

Storage product Business Group

Micron Technology