In-depth mining of special function register addresses of S3C2440

In-depth mining of special function register addresses of S3C2440

S3C2440 integrates multiple peripheral controllers (LCD controller, USB device controller, USB host controller, NAND Flash Controller, I2C controller, and SPI Controller ). To control these peripherals, you must set the registers of the corresponding controller to generate the corresponding driver sequence. Learn how to configure registers in S3C2440.

The address of the special function register of S3C2440 is as follows:

# Define rbankcon0 (x (volatileunsigned *) 0x48000004) // boot ROM control

# Define rbankcon1 (* (volatileunsigned *) 0x48000008) // bank1 Control

# Define rbankcon2 (* (volatileunsigned *) 0x4800000c) // bank2 cControl

......

In the course of study, I have been wondering why these addresses are like this. Once I think about it, I find information online, but I don't get any good results every time. I recently learned about AMBA (advancedmicrocontroller bus architecture) and finally solved this mystery. Haha !!!

Let's take a look at the figure below. It is estimated that we will be half done after reading it.

Figure 1 memory ing

The following is a detailed analysis.

Figure 2 Structure of S3C2440

First introduce AMBA. AMBA (advanced micro-controller bus architecture) is an on-chip bus specification launched by arm limited. It is currently the mainstream standard for Chip Bus. At first, AMBA 1.0 only had ASB and APB. In order to save the area, the bus protocol at this time adopted a three-state bus. In later versions of AMBA 2.0, AHB Bus was added, three bus groups are defined: advancedhigh Performance Bus (AHB), advancedsystem bus (ASB), and peripheral bus (Advanced
Peripheralbus, APB ).

Figure 3 typical AMBA-Based System

More information about the AMBA bus can be viewed online. There are many Chinese documents. Figure 2 shows that LCD controller, interrupt controller, USB host controller, power management, Nand controller, camera controller, memory controller, and AHB to APB bridge and DMA controller are mounted on the AHB Bus. UART Controller, I2C controller, USB device controller, i3s controller SDI/MMC controller, gpio, watchdog/Timer, RTC, ADC, SPI, and ac97 are mounted on the APB bus. The following section is taken from the S3C2440 chip manual:

The s3c2440a holds 13 bus masters. They include dramrefresh controller, LCD _dma, camif DMA, dma0, dma1, dma2, dma3, usb_host_dma, ext_bus_master, test interface controller (TIC) and ARM920T.

S3c2440a has 13 main devices. When the master device on the AHB Bus reads and writes data from the device, the address sent by the decoder of the AHB Bus (through the memory ing table) generates the signal corresponding to the address selected from the device and selects the device from the device; in this way, you can read and write from the device.

Figure 4 AHB Decoder

Figure 5 implementation code of the decoder

The memory ing table of the decoder is relatively independent. If the slave device on the AHB Bus changes, you must modify the memory ing table to ensure that each address corresponds to the correct slave device. The following is an example of a memory ing table.

Figure 6 memory ing table

Two memory ing tables are used: Memory ing tables under normal operation and memory ing tables during restart. During normal operation, the microprocessor's slave device includes internal RAM, external Ram, external ROM and AHB/APB bridge. When the system restarts, the system's memory ing does not include internal RAM, instead, the memory address segments from 0x0000-0000 to 0x0000-03ff are mapped to Nash. This part contains the system startup and initialization code. After the system starts initialization, The AMBA bus generates a remap signal and sends it to the decoder. The current memory ing table of the decoder is changed to the memory ing table under normal working conditions.

Below is the address ing of S3C2440

AHB Memory Map

Memory Control 0x48000000 0x48000030

USB Host 0x49000000 0x49000058

Interrupt 0x4a000000 0x4a00001c

DMA 0x4b000000 0x4b0000e0

Clock & Power Management 0x4c000000 0x4c000018

* LCD controller 0x4d000000 0x4d000060 0x4d000400 (palettestart address)

NAND Flash 0x4e000000 0x4e00003c

Camera interface 0x4f000000 0x4f0000a0

APB Memory Map

Uart0 0x50000000 0x50000028

Uart1 0x50004000 0x50004028

Uart2 0x50008000 0x50008028

PWM timer 0*51000000 0x51000040

USB device 0x52000140 0x5200026c

Watch Dog Timer 0x53000000 0x53000008

IIC 0x54000000 0x54000010

IIS 0x55000000 0x55000010

Ac97 0x5b000000 0x5b00001c

I/O port

• A 0x560000000x56000004
• B 0x560000040x56000018
• C 0x560000200x56000028
• D 0x560000300x56000038
• E 0x560000400x56000048
• F 0x560000500x56000058
• G 0x560000600x56000068
• H 0x560000700x56000078
• J 0x561_d0 0x561_d8
• Other 0x56000080 0x5620.cc

RTC 0x57000040 0x57000088

ADC 0x58000000 0x58000014

SPI 0x59000000 0x59000034

SD interface 0x5a0000000x5a000040

Summary: The decoder on the AHB Bus generates the chip selection Signal Based on the address and selects the corresponding device. There is an AHB to APB Bridge on the AHB Bus. The bridge is the slave device of the AHB Bus and the only main device on the APB bus. Bridge is a protocol converter (conversion from the AHB protocol to the APB Protocol). It also needs to complete the address decoding of the APB bus.