Each instruction will read or modify portions of the processor state
2. "Programmer":It can be the person who writes the program with the assembler code, or the compiler that produces the machine-level code.
3. Specific processor status: similar to IA32The Y86 program uses virtual addresses to refer to memory locations, and hardware and operating system software unite to translate virtual addresses into actual or physical addresses
5. Status Code STATIt indicates the overall state of the program execution, indicating whether it is functioning correctly or that an exception has occurred.
Second, Y86 directiveThe Y86 instruction set is basically a subset of the IA32 instruction set, including only four-byte integer operations, with less addressing and fewer operations.
Refer to the 232 page of the textbook for the reference and byte encoding of sinks.
1.MOVL instructionIA32 's MOVL directive is divided into four types:
irmovl,rrmovl,mrmovl,rmmovl
The preceding two letters are in the format of the specified source operand and the destination operand explicitly, the first bit is the source operand, and the second bit is the destination operand.
(1) Number of source operationsCan be:
(2) Purpose of operationi-立即数r-寄存器m-存储器
Can be:
r-寄存器m-存储器
※ The memory reference method here is a simple base address and offset form, and the addressing method does not support the scaling of the second variable address register and any register value.
※ Two operands cannot be from the memory, nor allow the immediate number to be transmitted to the memory.
2. Four integer operation instructionsaddl 加subl 减andl 与xorl 异或
And they operate only on register data (as distinct from IA32, which also allows these operations on the memory data).
These instructions will set up three condition codes :
3. Seven Jump Commands--branch controlZF-零 SF-符号OF-溢出
4. Six Conditional delivery Instructionsjmp 直接跳转jle（SF^OF）|ZF 有符号数≤jl SF^OF 有符号＜je ZF 相等/零jne ~ZF 不相等/非零jge ~(SF^OF) 有符号≥jg ~(SF^OF)&~ZF 有符号＞
cmovlecmovlcmovecmovnecmovgecmovg
The format of these instructions is the same as the Register-register transfer Directive , but the value of the destination register is updated only if the condition code satisfies the required constraint RRMOVL.
5.call and RETThe call instruction returns the address to the stack, and then jumps to the destination address, which is returned from such a procedure invocation.
6.PUSHL and POPLImplement in-stack and out-stack
7.halt instructionThe halt instruction stops the execution of the instruction, which causes the processor to stop and the status code to be set to HLT.
The analogy ia32:hlt directive is similar, but the IA32 application does not allow this instruction because it causes the entire system to pause.
Third, byte-level encoding of instructionsEach instruction requires a range of 1-6 bytes, and the first byte of each instruction indicates the type of instruction .
1. First byteThis byte is divided into two parts, each part 4 bits:
For example: the No. 233 page of the textbook, the function Code of the Y86 instruction set:
The code portion of the integer operation is 6, the functional part distinguishes ADDL,SUBL,ANDL,XORL
The code portion of the branch instruction is 7.
The code portion of the delivery instruction is 2.
It's important to note that RRMOVL is in the delivery instructions, which says they have the same instruction code.
Each of the 8 program registers has a corresponding 0~7 register identifier , and the program register exists in a register file in the CPU, which is a small, random-access memory with the Register ID as the address.
When you need to indicate that no registers should be accessed, use the ID value 0xF to indicate
2. Some require extra bytes (1) Additional Register indicator bytesSpecify one or two registers, such as RA or RB.
The use of this word:
1.irmovl的立即数数据2.rmmol和mrmovl的地址指示符的偏移量3.分支指令和调用指令的目的地址
Precautions
1.分支指令和调用指令的目的地址是一个绝对地址2.所有整数采用小端法编码
※ Important properties of instruction set:
Byte encoding must have a unique explanation
Exercise 4.1: This problem only need to follow the instructions to encode the values of each bit to correspond, such as the first line, IRMOVL instruction is 30f, the purpose of the operation is%EBX, check the table is 3, the source operation is immediately number 15, converted to 16 into the xx xx 0f, the small-end method is expressed as 0f 00 00 00, combined together that is 30f30f000000.
Iv. Y86 anomalies 1. Possible value of status code statExercise 4.2: This problem should be careful to divide the numbers into different instructions.
Stat describes the overall state of the program execution
2. When an exception occurs?1. AOK 正常操作2. HLT 处理器执行halt指令3. ADR 遇到非法地址4. INS 遇到非法指令
The y86--processor stops running instructions.
V. Y86 proceduresMore complete? Call an exception handler
See textbook 第238-239 page for specific examples
In contrast to the Y86 and IA32 codes, they are essentially the same, but:
The difference between 1.y86 and IA322. Note Some of the following:1.Y86有时需要两条指令来完成IA32一条指令就能完成的事2.Y86没有伸缩寻址模式
(1) The command indicates where the code or data should be placed, and how it should be aligned
(2) to "." The beginning is the assembler command
(3) The only tool for creating Y86 code is the assembler, so programmers must perform tasks that would normally be done to compilers, linker, and runtime systems.
Vi. details of some Y86 directivesSpecifically POPL and PUSHL, there are two different conventions when pressing/ejecting the stack pointer%esp:
1.压入/弹出%esp的原始值2.压入/弹出%esp-/+4后的值
After testing, it is found that the default press-in pops up the original values .
Section II Logic Design and hardware control Language HCLPUSHL There is ambiguity between the different x86 models, but POPL does not.
In electronic circuits, the logic 1 is represented by a high voltage of about 1.0V, and the logic 0 is represented by a low voltage of about 0.0V.
First, the logic gate1. The output generated by the logic gates is a Boolean function that equals their input bit value.
2.
AND &&OR ||NOT !
3. The logic gate operates only on the number of individual bits , not the entire word.
4. The logic gate is always active, and the input change output quickly follows the change.
Ii. combinational Circuits and HCl Boolean expressions1. Limitations when building compute blocks (combinational circuits)Combinational logic circuit corresponding to EDA learning
There are a few bits and pieces of knowledge that need to be noticed:
The multiplexed function is described by a case expression, in the following format:
[select_1 : expr_1select_2 : expr_2……]Logically, these selection expressions are evaluated sequentially .
Allow non-mutex between different selection expressions
The general format for judging set relationships is:
in {iexpr1,iexpr2,...,iexprk}
IEXPR, etc. are all integer expressions.
V. Memory and Clock1. Two types of memory devices for sequential circuits:Sequential logic circuit corresponding to EDA learning
(1) Clock Register (register): stores a single bit or word.
(2) Random access storage (for short): store multiple words, use the address to choose which word to read/write.
2.Y86 processorThe registers are divided into "hardware registers" and "program registers".
It will save the program counter PC with the clock register, the condition code CC and the program status Stat.
The sequential implementation of the third section Y86This section of the study compares the rules of the Verilog language learned in the EDA course, much the same, but pay attention to the migration--the operation that corresponds to the instruction in place.
SEQ Processor
First, the process of organizing into phase (i) six basic stages:(ii) The specific framework is divided into four categories: 1. For OPL (integer and logical Operations), RRMOVL (register-register transfer) and IRMOVL (Immediate-register-transfer) 2. For RMMOVL and Mrmovl3. For the PUSHL and Popl4. For jump, call and ret two , SEQ hardware structure 1.SEQ Abstract view of the drawing:Each phase of the implementation of the content is shown in page 250, according to each step of the calculation of the topic in the 253-page Exercise 4.11, the most important thing to do this problem is to pay attention to the meaning of each character represents what, in order to do the correct calculation. This problem is not difficult, is a bit of trouble, more read more understanding.
There are six basic stages, see above. Refer to the 258-page diagram for specific links.
Iii. timing of SEQThe SEQ implementation includes combination logic and two memory devices :
1.时钟寄存器——程序计数器和条件码寄存器2.随机访问存储器——寄存器文件、指令存储器和数据存储器
For the five hardware units mentioned above, it can be divided into two categories:
1.组合逻辑——指令存储器2.时序——剩下四个
The remaining four:
条件码寄存器——只在执行整数运算指令时装载数据存储器——只在执行rmmovl、pushl或call时写入寄存器文件——两个写端口允许每个时钟周期更新两个程序寄存器。特殊寄存器？0xF表示此端口不应执行写操作。
Organizational principles under the ※y86 instruction set:
The summary is that the clock is used to control the updating of the state elements, and the values are propagated by the combinatorial logic.
Iv. realization of the SEQ stageConstants that must be explicitly referenced in the control logic:
Halt directive: Causes the processor state to become hlt, causing it to stop running
1. Taking the finger stageTake the PC as the first byte and read 6 bytes.
Two logical blocks (separated from the first byte, four bits each)
icode-指令代码ifun-指令功能Three-bit signals (based on icode values)
instr_valid-发现不合法的指令need_regids-包含寄存器指示符字节吗need_valC-包括常数字吗The latter five bytes are the combined encoding of the Register designator byte and the constant number.
All need to access the register file, according to the case of four ports, determine which register should be read to generate the signal Vala, VALB
3. Implementation phase(1) including the Arithmetic/logic unit ALU, the output is Vale.
Alu is often used as an adder
(2) including the condition Code register
4. The stage of the visit0, sign, overflow, generate signal set_cc
Two data blocks generate the memory address and the value of the memory input evidence, and two generate control signals indicating whether to read or write.
The new value of the program counter is generated. Resources
Textbooks.
ExperimentAfter you run the make command
To view the contents of the directory, you can see only. ys files
After compiling with the make all command
After compiling and viewing the contents of the directory, you can see that there are already compiled. yo files that can be viewed with vim
The code in Figure 4-7 of the No. 239 page of the textbook, called Asum.yo in the system, prints its contents on the screen:
It can be seen that the results are consistent with the 240 pages of the textbook.
Textbook page No. 251 of Figure 4-17, I first used to build a 417.ys enter after entering:
Then compile with make 417.yo and use Vim to enter 417.yo after compiling.
Each instruction will read or modify portions of the processor state
2. "Programmer":It can be the person who writes the program with the assembler code, or the compiler that produces the machine-level code.
3. Specific processor status: similar to IA32The Y86 program uses virtual addresses to refer to memory locations, and hardware and operating system software unite to translate virtual addresses into actual or physical addresses
5. Status Code STATIt indicates the overall state of the program execution, indicating whether it is functioning correctly or that an exception has occurred.
Second, Y86 directiveThe Y86 instruction set is basically a subset of the IA32 instruction set, including only four-byte integer operations, with less addressing and fewer operations.
Refer to the 232 page of the textbook for the reference and byte encoding of sinks.
1.MOVL instructionIA32 's MOVL directive is divided into four types:
irmovl,rrmovl,mrmovl,rmmovl
The preceding two letters are in the format of the specified source operand and the destination operand explicitly, the first bit is the source operand, and the second bit is the destination operand.
(1) Number of source operationsCan be:
(2) Purpose of operationi-立即数r-寄存器m-存储器
Can be:
r-寄存器m-存储器
※ The memory reference method here is a simple base address and offset form, and the addressing method does not support the scaling of the second variable address register and any register value.
※ Two operands cannot be from the memory, nor allow the immediate number to be transmitted to the memory.
2. Four integer operation instructionsaddl 加subl 减andl 与xorl 异或
And they operate only on register data (as distinct from IA32, which also allows these operations on the memory data).
These instructions will set up three condition codes :
3. Seven Jump Commands--branch controlZF-零 SF-符号OF-溢出
4. Six Conditional delivery Instructionsjmp 直接跳转jle（SF^OF）|ZF 有符号数≤jl SF^OF 有符号＜je ZF 相等/零jne ~ZF 不相等/非零jge ~(SF^OF) 有符号≥jg ~(SF^OF)&~ZF 有符号＞
cmovlecmovlcmovecmovnecmovgecmovg
The format of these instructions is the same as the Register-register transfer Directive , but the value of the destination register is updated only if the condition code satisfies the required constraint RRMOVL.
5.call and RETThe call instruction returns the address to the stack, and then jumps to the destination address, which is returned from such a procedure invocation.
6.PUSHL and POPLImplement in-stack and out-stack
7.halt instructionThe halt instruction stops the execution of the instruction, which causes the processor to stop and the status code to be set to HLT.
The analogy ia32:hlt directive is similar, but the IA32 application does not allow this instruction because it causes the entire system to pause.
Third, byte-level encoding of instructionsEach instruction requires a range of 1-6 bytes, and the first byte of each instruction indicates the type of instruction .
1. First byteThis byte is divided into two parts, each part 4 bits:
For example: the No. 233 page of the textbook, the function Code of the Y86 instruction set:
The code portion of the integer operation is 6, the functional part distinguishes ADDL,SUBL,ANDL,XORL
The code portion of the branch instruction is 7.
The code portion of the delivery instruction is 2.
It's important to note that RRMOVL is in the delivery instructions, which says they have the same instruction code.
Each of the 8 program registers has a corresponding 0~7 register identifier , and the program register exists in a register file in the CPU, which is a small, random-access memory with the Register ID as the address.
When you need to indicate that no registers should be accessed, use the ID value 0xF to indicate
2. Some require extra bytes (1) Additional Register indicator bytesSpecify one or two registers, such as RA or RB.
The use of this word:
1.irmovl的立即数数据2.rmmol和mrmovl的地址指示符的偏移量3.分支指令和调用指令的目的地址
Precautions
1.分支指令和调用指令的目的地址是一个绝对地址2.所有整数采用小端法编码
※ Important properties of instruction set:
Byte encoding must have a unique explanation
Exercise 4.1: This problem only need to follow the instructions to encode the values of each bit to correspond, such as the first line, IRMOVL instruction is 30f, the purpose of the operation is%EBX, check the table is 3, the source operation is immediately number 15, converted to 16 into the xx xx 0f, the small-end method is expressed as 0f 00 00 00, combined together that is 30f30f000000.
Iv. Y86 anomalies 1. Possible value of status code statExercise 4.2: This problem should be careful to divide the numbers into different instructions.
Stat describes the overall state of the program execution
2. When an exception occurs?1. AOK 正常操作2. HLT 处理器执行halt指令3. ADR 遇到非法地址4. INS 遇到非法指令
The y86--processor stops running instructions.
V. Y86 proceduresMore complete? Call an exception handler
See textbook 第238-239 page for specific examples
In contrast to the Y86 and IA32 codes, they are essentially the same, but:
The difference between 1.y86 and IA322. Note Some of the following:1.Y86有时需要两条指令来完成IA32一条指令就能完成的事2.Y86没有伸缩寻址模式
(1) The command indicates where the code or data should be placed, and how it should be aligned
(2) to "." The beginning is the assembler command
(3) The only tool for creating Y86 code is the assembler, so programmers must perform tasks that would normally be done to compilers, linker, and runtime systems.
Vi. details of some Y86 directivesSpecifically POPL and PUSHL, there are two different conventions when pressing/ejecting the stack pointer%esp:
1.压入/弹出%esp的原始值2.压入/弹出%esp-/+4后的值
After testing, it is found that the default press-in pops up the original values .
Section II Logic Design and hardware control Language HCLPUSHL There is ambiguity between the different x86 models, but POPL does not.
In electronic circuits, the logic 1 is represented by a high voltage of about 1.0V, and the logic 0 is represented by a low voltage of about 0.0V.
First, the logic gate1. The output generated by the logic gates is a Boolean function that equals their input bit value.
2.
AND &&OR ||NOT !
3. The logic gate operates only on the number of individual bits , not the entire word.
4. The logic gate is always active, and the input change output quickly follows the change.
Ii. combinational Circuits and HCl Boolean expressions1. Limitations when building compute blocks (combinational circuits)Combinational logic circuit corresponding to EDA learning
There are a few bits and pieces of knowledge that need to be noticed:
The multiplexed function is described by a case expression, in the following format:
[select_1 : expr_1select_2 : expr_2……]Logically, these selection expressions are evaluated sequentially .
Allow non-mutex between different selection expressions
The general format for judging set relationships is:
in {iexpr1,iexpr2,...,iexprk}
IEXPR, etc. are all integer expressions.
V. Memory and Clock1. Two types of memory devices for sequential circuits:Sequential logic circuit corresponding to EDA learning
(1) Clock Register (register): stores a single bit or word.
(2) Random access storage (for short): store multiple words, use the address to choose which word to read/write.
2.Y86 processorThe registers are divided into "hardware registers" and "program registers".
It will save the program counter PC with the clock register, the condition code CC and the program status Stat.
The sequential implementation of the third section Y86This section of the study compares the rules of the Verilog language learned in the EDA course, much the same, but pay attention to the migration--the operation that corresponds to the instruction in place.
SEQ Processor
First, the process of organizing into phase (i) six basic stages:(ii) The specific framework is divided into four categories: 1. For OPL (integer and logical Operations), RRMOVL (register-register transfer) and IRMOVL (immediate count-register transfer) 2. For RMMOVL and MRMOVL 3. For PUSHL and POPL 4. For jump, call and RETEach phase of the implementation of the content is shown in page 250, according to each step of the calculation of the topic in the 253-page Exercise 4.11, the most important thing to do this problem is to pay attention to the meaning of each character represents what, in order to do the correct calculation. This problem is not difficult, is a bit of trouble, more read more understanding.
These four types can be set in a frame.
Second, the SEQ hardware structure 1.SEQ Abstract view of the drawing:There are six basic stages, see above. Refer to the 258-page diagram for specific links.
Iii. timing of SEQThe SEQ implementation includes combination logic and two memory devices :
1.时钟寄存器——程序计数器和条件码寄存器2.随机访问存储器——寄存器文件、指令存储器和数据存储器
For the five hardware units mentioned above, it can be divided into two categories:
1.组合逻辑——指令存储器2.时序——剩下四个
The remaining four:
条件码寄存器——只在执行整数运算指令时装载数据存储器——只在执行rmmovl、pushl或call时写入寄存器文件——两个写端口允许每个时钟周期更新两个程序寄存器。特殊寄存器？0xF表示此端口不应执行写操作。
Organizational principles under the ※y86 instruction set:
The summary is that the clock is used to control the updating of the state elements, and the values are propagated by the combinatorial logic.
Iv. realization of the SEQ stageConstants that must be explicitly referenced in the control logic:
Halt directive: Causes the processor state to become hlt, causing it to stop running
1. Taking the finger stageTake the PC as the first byte and read 6 bytes.
Two logical blocks (separated from the first byte, four bits each)
icode-指令代码ifun-指令功能Three-bit signals (based on icode values)
instr_valid-发现不合法的指令need_regids-包含寄存器指示符字节吗need_valC-包括常数字吗The latter five bytes are the combined encoding of the Register designator byte and the constant number.
All need to access the register file, according to the case of four ports, determine which register should be read to generate the signal Vala, VALB
3. Implementation phase(1) including the Arithmetic/logic unit ALU, the output is Vale.
Alu is often used as an adder
(2) including the condition Code register
4. The stage of the visit0, sign, overflow, generate signal set_cc
Two data blocks generate the memory address and the value of the memory input evidence, and two generate control signals indicating whether to read or write.
The new value of the program counter is generated.
Learning SummaryThe content of this chapter is generally unfamiliar, looks very laborious, only to the textbook stumbling to do, the ability to migrate out is not enough, but the middle of the logic gate calculation of the part because the last semester has Verilog Language Foundation, learning can be used as an analogy, extrapolate, Thus the understanding of this part is relatively easy.
ResourcesTextbooks.
ExperimentAfter you run the make command
To view the contents of the directory, you can see only. ys files
After compiling with the make all command
After compiling and viewing the contents of the directory, you can see that there are already compiled. yo files that can be viewed with vim
The code in Figure 4-7 of the No. 239 page of the textbook, called Asum.yo in the system, prints its contents on the screen:
It can be seen that the results are consistent with the 240 pages of the textbook.
Textbook page No. 251 of Figure 4-17, I first used to build a 417.ys enter after entering:
Then compile with make 417.yo and use Vim to enter 417.yo after compiling.
Reference, I saw Shang she summed up than I have more organized.
Information security system Design Fundamentals Fifth Week study summary------20135334 Zhao Yanglin
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