Ing between physical and virtual addresses of Au1200 SOC and norflash

Reference document: auw._datasheet.pdf, ml2010-0129.pdf (Meiling project circuit diagram), s29gl064n90tfi04 flash Datasheet

 

 

 

The above is the structure/interface of the Au1200 SOC, where the upper left corner is the mips32 core (au1 core), and other modules are the peripheral controllers on various SOC chips, all these in-chip modules are connected and communicated through the system bus and peripheral bus in the SOC.

As a typical cpu Of The mips32 architecture, au1 core features comply with the description in the see mips run, 2nd document, here, refer to the basic concepts and diagrams of the mips architecture address space described in section 2.8. Any address used in a program (even an executable binary program that has been compiled, compiled, and linked, whether it is an application or a system program) is a virtual address, when MIPS-core reads machine commands of these programs, these virtual addresses must be converted through a specific address ing mechanism (not necessarily through MMU ), therefore, the data bus of au1 core sends the physical address to the system bus of SOC. Although the address ing mechanism of MIPs is different from that of X86, the conversion from virtual addresses to physical addresses in some areas of the VM is very simple, but the value of virtual addresses and physical addresses must be different.

The MIPs CPU running status is also divided into the user and kernel states. However, unlike the kernel/user State mechanisms of other processors, when the mips architecture switches from the kernel to the user State, except that the application cannot access the 2 GB area of the virtual address space (the highest bit of the virtual address is 1), otherwise an error will occur, causing the trap. The virtual address space displayed by the program is displayed as follows:

• Kuseg (0x0000 0000 ~ 0x8000 0000)

  -- This is the VM that the application can use. All VPNs in the region need to be mapped through MMU. Therefore, the reference to the region address must first ensure MMU (or other specific address ing agencies) it has been correctly set (and this work is usually done by the OS kernel), so this region is not accessible in the program before the OS kernel is fully started;

• Kseg0 (0x8000 0000 ~ 0x0000)

  -- The ing between the virtual address and the physical address in this region is very simple. You can directly increase the virtual address by 3 points and zero. However, the MIPs design scheme stipulates that the addresses in this region are all accessed through the cache, so this region is also unavailable before the cache Initialization is set. For systems with MMU, this region address is often used in OS kernel code.

 

• Kseg1 (0xa000 0000 ~ 0x0000)

  -- Same as the kseg0 region,

  The ing between the virtual address and the physical address in this region is still to directly increase the virtual address by 3 and zero, and the access to the address in this region no longer needs to be cached.The kseg1 region is the only VM region that can be directly accessed by the program when the MIPs core processor is started.

  . The virtual address of the First Command executed after the MIPs core CPU is powered on is 0xbfc0 0000, which is, and must be located in the kseg1 region. After the address is mapped by the address of the mips architecture, the corresponding physical address is0x1fc0 0000

  .

  At the same time, the hardware connection must also ensure that the system startup code (yamon, uboot, etc.) in the storage device (norflash, or ROM) is located at the position corresponding to 0x1fc0 0000
  --Note that it is "corresponding", not "yes"
  

  That is, after the system is powered on, the physical address transmitted to the norflash device address bus is not 0x1fc0 0000. In the Au1200 SoC hardware environment used in this project, after the system is powered on, the address signal transmitted to the norflash address bus is determined by the norflash address bus width and the SRAM controller. For more information, see

 

• Kseg2 (0xc000
  0000 ~ 0 xFFFF FFFF)

  -- The VM region that the program can access in the MIPs CPU kernel state. Generally, only the OS kernel code will use the address of this region. The address of this region also needs to be mapped through MMU, therefore, it must be available after MMU Initialization is complete.

 

Au1200
In SOC, The Au1-Core converts a 32-bit virtual address to a 36-bit physical address to the system bus (datasheet, 2.5 ), the 36-bit physical bus of system bus is reused by the 36-BITs address bus sysbus_addr [35: 0] and the 32-Bits Data Bus sysbus_data [31: 0.

In the Au1200 SOC, Flash, Rom, and other peripherals are controlled and connected through the on-chip SRAM controller. The SRAM controller description is located in section 3.2 of datasheet. It consists of four chip selects. In the diagram of the Meiling project, the four chip selection signals correspond to au_cs0 ~ Au_cs3 pin, we use au_cs0 as the norflash chip enabling (see the schematic P7 ).

For sysbus_addr [36],

For the value of sysbus_addr [35: 32], see Au1200 datasheet. Table 20. We use the SRAM controller to connect to norflash. Therefore, for norflash, the upper or lower four bits in the 36-bits physical address passed by system bus are 0.

 

The various signals sent to norflash are described in Au1200 datasheet 3.2.5 when the SRAM Controller connects to norflash. The Rad [] is the address signal that the Au1200 SOC actually sends to the norflash physical device.

, Rad [] corresponds to the 15 pins in the diagram of the Meiling project au_addr. Due to the address Lock Mechanism Implemented in the SRAM controller (datasheet 3.2.2 ),The address data sent from the Au1200 SOC to the norflash and Rom devices can reach 30 bits, that is, the norflash device with a maximum capacity of 1 GB can be addressable, the 30 BITs address value is the low 30 bits of the 36-bits physical address passed to the SRAM controller by the system bus in the SOC, which is sent twice to the address pin of the norflash physical peripherals.

 

In the Meiling project,
We use
8 Mb norflash (model: s29gl064n90tfi04, where 64 represents 64 Mbit) is based on the word (16
BITs) addressing, and because we are in the circuit design, the byte # pin of norflash is pulled high, so every norflash read/write is 2 bytes of data (see Flash datasheet ). Therefore, we use a total of 22 actual address pins (A0 ~ A21)
, 222
* 2 bytes = 8 Mb, that is, the address bus of norflash is 23 bits. The A23 identified in the circuit schematic diagram is actually invalid, just for the consistent encapsulation of a series of norflash, generally, the number of address pins encapsulated by this series of norflash is unified into the number of address pins of the series of large capacity norflash.

 

We only use 22 bits in the 30-BITs address sent from the SRAM controller through the rad [] + lock,
Corresponds toAu_addr1 ~ Au_addr14

And latch_addr15 ~ Latch_addr22

.

The original circuit of the Meiling Project
As shown in Figure Page 7, we have added an address latch sn74lvc16374adggr to lock the memory.

Au_addr [0: 7] In au_addr [0: 15], which is the low 8-bit physical address of 15-bits sent by the SRAM controller through the internal lock mechanism.

Au_addr [1: 14]
And latch_addr []

These 22 pins correspond to

In sysbus_addr [0: 35]

Sysbus_addr [:22]

, Corresponding to a0 ~ connected to the norflash peripherals ~ A21 these 22 pins.

Why do we connect au_addr1 to A0 instead of au_addr0 to A0? This is because the norflash we use uses the word (16 bits) Addressing, while the virtual address space facing the program is addressable in 8-bits bytes, assume that the program needs to operate the byte data in the 0xbfd0 0000 and 0xbfd0 0001 addresses, but the two 8-bits data in norflash is actually the data in the same 16-bits unit, therefore, we use

0xbfd0
The addresses 0000 and 0xbfd0 0001 must correspond to the same basic data unit in norflash.

Au_addr1
Connect to the A0 pin to achieve this goal.

 

 

 

Finally, Let's explain the program (here the "program" includes typical applications running on the machine, flash_eraseall, flashcp, and other Flash software, as well as BDI built-in software, when using commands such as erase, prog, and go in the BDI console, the virtual address is used directly.

) How is the system power-on start address 0xbfc0 0000 mapped to norflash a0 ~ Step by Step ~ A21 on these 22 pins:

1. The virtual address 0xbfc0 0000 In the VM goes through au1 core to output 36-bits 0x0 1fc0 0000 to the sysbus_addr [35: 0] of the system bus in the SOC and sends it to the SRAM controller.

2. The SRAM controller uses the low 30-bits of 0x0 1fc0 0000, that is, 0x1fc00000 (01 1111 1100 0000 0000 0000 0000 = 0000 011111110000000) through rad [] (that is, the Au1200 SOC

   Au_addr [0: 14]
   This group of 15 pins) are sent twice through the lock mechanism

   ---- The tasks above this are completed in the Au1200 SoC chip ----

3. External address latches on Meiling PCB

   Sn74lvc16374adggr

   Au_addr [0: 14] au_addr [0: 7] of the second output address signal of this pin, corresponding

   (0x1fc00000 =

   011111110000000
   000000000000000

   ) In (
   10000000

   )

   Locks and is sent out by latch_addr;

4. SOC

   
   Au_addr [] au_addr [],

   Corresponds to (0x1fc00000
   =

   011111110000000
   000000000000000

   ) In (

   00000000000000

   ) Directly connect to the a0 ~ of norflash ~ A13 pin

5. Based on Steps 3 and 4, the norflash address bus pin A21 ~ The corresponding potential value on A0 should be (
   10000000

   00000000000000

   Medium; "> = 10 0000 0000 0000 0000

   )

   -- This is the address pin signal of 0xbfc0 0000, which corresponds to the address pin signal of the norflash physical device when the Au1200 is powered on.

In summary, the power-on start address corresponds to the address pin value of norflash (
Medium; "> 10 0000 0000 0000 0000 0000 = 0x20000
0) the identified physical address is located at the start of the last 4 MB in norflash. Note: The basic storage unit of norflash is 16 bits = 2 bytes, therefore, the norflash capacity after the power-on start address is (0x3fffff-0x200000 + 1) * 2 = 4 MB, which means the yamon Program executed as power-on, it should be stored in the starting position of the last 4 MB of norflash.

If norflash still maintains word addressing, when the norflash capacity changes to 4 MB, that is, the valid address pin of the norflash device changes to a0 ~ A20. Correspondingly, the address lock Au1200

SOC

Au_addr of the second output address signal [0: 6],

Eventually norflash
Address Bus pin A20 ~ The value corresponding to A0 should be (
Medium; "> 0 0000 0000 0000 0000

= 0x000000

),

That is, the starting point of norflash. At this time,
The yamon program should still be stored at the start of the last 4 MB of norflash, but the last 4 MB is the first 4 MB.
.

When the norflash capacity is less than 4 MB, no matter what the capacity is,

0xbfc0
0000 norflash corresponding to the power-on start address
Address Bus pin a0 ~ If the signal on an (n <20) is 0, the yamon program should be placed at the starting position of norflash.

Similarly, when the norflash capacity is increased to 16 MB,
Norflash
The valid device address pin is changed to a0 ~ A22,

Correspondingly, address locks
Au1200

SOC

Au_addr of the second output address signal [0: 8],

Final
Norflash
Address Bus pin A20 ~ The value corresponding to A0 should be (
Medium; "> 110 0000 0000 0000 0000

= 0x600000

),
After power-on start address
The norflash capacity of IS (0x7fffff-0x600000 + 1) * 2 = 4 MB
That is, the yamon program should still be saved at the starting point of the last 4 MB of norflash.

Similarly, if
When the norflash capacity is increased to 512 MB, it is assumed that the number of pins is sufficient,
Norflash
The valid device address pin is changed to a0 ~ A27,
Correspondingly, address latches lock Au1200

SOC

Au_addr In the second output address signal [],

Final
Norflash
Address Bus pin a27 ~ The value corresponding to A0 should be (
1111 1110 0000 0000 0000 0000 0000

= 0xfe00000

),
After power-on start address
The norflash capacity of IS (0 xfffffff-0xfe00000 + 1) * 2 = 4 MB,
That is, the yamon Program
It should still be stored in the starting position of the last 4 MB of norflash.

However, when the norflash capacity is increased to 1024 MB,
Norflash
The valid device address pin is changed to a0 ~ A28,
Address latches

SOC

All au_addr In the second output address signal [0: 14],
Final
Norflash
Address Bus pin A28 ~ The value corresponding to A0 should be (
0 1111 1110 0000 0000 0000 0000

= 0x0fe00000

).
After power-on start address
The norflash capacity of is changed to (0x1fffffff-0x0fe00000 + 1) * 2 = 516 MB.
Yamon program still
However, it should be stored in the starting position of the last 516mb of norflash. In this case, the maximum capacity that Au1200 can address through the SRAM controller is norflash.