After learning interfaces, we can find that many of the original tasks are programming interfaces :(
Pick up the code from everywhere and look at it. Alas, it's really easy!
I wrote some comments again to pave the way for future users ~
/**//*
Name: IRQ. c
Copyright: GPL
Author: raywill
Date: 22-12-06
Description: init, disable and enable interrupt procedure
*/
# Ifndef irq1_port
# Define irq1_port 0x21
# Define irq2_port 0xa1
# Endif
/**//*
About 8259a
1.8259a is the chip used to Manage interruptions in a PC. 8259 cannot be found in the actual PC motherboard,
This is because it is integrated into a large-scale chip, and its functions are equivalent to 8259.
As an oser, we can use a PC with 8259 chips.
2.8259 Initialization is required before work, including
1) interrupt request method setting (icw1)
2) set the interrupt type number (icw2)
3) interrupt cascade configuration (icw3)
4) Specific full nesting mode (icw4)
3. PIC port address
Master PIC command 0x20
Master pic data 0x21
Slave PIC command 0xa0
Slave PIC data 0xa1
4. Explanation of the operations in the init_irq () function
========================================================== =
Outportb (0x20, 0x11 );
*) Program icw1 using Port 20 h (A0 = 0)
*) 11 h = 000 1 0 0 1b
A7 ~ of D7-D5 000 interrupt vector address ~ A5
D4 = 1
D3 0 edge departure Input
D2 0 call interval is 8
D1 0 Cascade
D0 1 Write icw4
========================================================== =
Outportb (0x21, irq0_int );
Outportb (0xa1, irq8_int );
*) Program icw2 using port 21h (A0 = 1)
*) Irq0_int = 20 h = 00100 000b
D7-D3 00100 interrupt type number high 5-digit 100000 = 20 h
After this step, the ir0 interrupt number is 100000b = 20 h.
The interrupt Number of ir1 is 100000b = 21 h.
·······
The interrupt Number of ir7 is 100000b = 27 h.
D2-D0 000 low three-digit interrupt type number, from hardware ir0 ~ Provided by ir7
*) Irq8_int = 28 h = 00101 000b;
D7-D3 00101 interrupt type No. Height 5-bit 101000 = 28 h
After this step, the ir8 interrupt number is 100000b = 28 h.
The interrupt number corresponding to ir9 is 100000b = 29 H.
·······
The interrupt Number of ir15 is 100000b = 2fh.
D2-D0 000 low three-digit interrupt type number, consisting of hardware ir8 ~ Provided by ir15
========================================================== =
Outportb (0x21, 0x04); // programming the master chip (master)
Outportb (0xa1, 0x02); // programming the slave
*) Program icw3 using port 21h (A0 = 1)
*) Icw3 must be set only when it is configured as cascade mode.
*) The main and slave ICWs have different meanings.
*) Main chip
04 H = 00000010b
1) D7-D0 00000010 int cascade mask, second S1 = 1 indicates that the slave is connected to the master chip through the ir1 pin
*) Slave slice
02 h = 00000 010
1) D7-D3 00000 reserved, all set to zero
2) D2-D0 010 indicates the starting chip of the int signal connected to the main chip of the several pins,
010b indicates the 2 pin, exactly corresponding to the 04h in the main chip
========================================================== =
Outportb (0x21, 0x01 );
Outportb (0xa1, 0x01 );
*) 01 H = 000 0 00 0 1
D7-D5 000 is forced to 0
D4 0 non-special full nesting mode
D3-D2 00 non-buffering Mode
D1 0 normal EIO (the interrupt end command must be added at the end of the interrupt)
D0 1 MCS 8086/88 Mode
========================================================== =
5. Summary of the above process
Init_irq mainly does the following:
1) redirect the position of the interrupt vector
The default (BIOS-defined) vector offsets are 8 for Master PIC and 0x70 for slave PIC:
MASTER: IRQ 0 .. 7-> Int 8 .. 0xf (vector offset = 0x08)
SLAVE: IRQ 8... 15-> int 0x70 .. 0x77 (vector offset = 0x70)
However, these default values don't suit the needs of protectedmode programming: There's a collision between irqs 0 .. 7 (mapped to Int 8 .. 0xf) and processor exceptions (INT 0 .. 0x1f are reserved ). consequently you wouldn't be able to tell the difference between an IRQ or an software error.
2) perform cascade programming to determine the Working Mode
6. After the ICW Initialization is complete, the OCW command can be sent to the PIC to initialize the interrupt shielding word.
Master pic data 0x21
Slave PIC data 0xa1
DI = 1 indicates the I-related interrupt, and di = 0 indicates that the corresponding interrupt is disabled.
The code in maray is:
// Disable all interrupt first
Outportb (0x21 ,~ 0x00 );
Outportb (0xa1 ,~ 0x00 );
*/
Void init_irq ()
...{
Static const unsigned irq0_int = 0x20, irq8_int = 0x28;
/**//**/
/** // * Initialization control word #1 (icw1 )*/
Outportb (0x20, 0x11 );
Outportb (0xa0, 0x11 );
/** // * Icw2:
Route irqs 0-7 to ints 20 h-27 H */
Outportb (0x21, irq0_int );
/** // * Route irqs 8-15 to ints 28h-2fh */
Outportb (0xa1, irq8_int );
/** // * Icw3 */
Outportb (0x21, 0x04 );
Outportb (0xa1, 0x02 );
/** // * Icw4 */
Outportb (0x21, 0x01 );
Outportb (0xa1, 0x01 );
/** // * Enable irq0 (timer) and irq1 (keyboard )*/
Outportb (0x21 ,~ 0x00);/** // * Only keyboard for testing */
Outportb (0xa1 ,~ 0x00 );
Kprintf ("8259 init OK! ");
}
Void enable_irq (int irq)
...{
/** // * Two case: IRQ <8, IRQ> = 8 */
Byte bit = 1;
If (IRQ> (15 + irq_offset) | IRQ <(0 + irq_offset) return;
Bit <= IRQ % 8;
If (IRQ <(8 + irq_offset ))...{
Outportb (irq1_port ,~ Bit & inportb (irq1_port ));
} Else ...{
Outportb (irq2_port ,~ Bit & inportb (irq2_port ));
}
}
Void disable_irq (int irq)
...{
/** // * Two case: IRQ <8, IRQ> = 8 */
Byte bit = 1;
If (IRQ> (15 + irq_offset) | IRQ <(0 + irq_offset) return;
Bit <= IRQ % 8;
If (IRQ <(8 + irq_offset ))...{
Outportb (irq1_port, bit | inportb (irq1_port ));
} Else ...{
Outportb (irq2_port, bit | inportb (irq2_port ));
}
}
