Integrated Circuit Intro

1, Noise Margin

Both TTL and CMOS Logic level have thresholds. For example, 5V CMOS Vouth > 4.4V, Voutl <0.33V; and its corresponding input level Vinh >3.5, Vinl <1.5v. So, here 5V COMs's noise margin is vnh=4.4-3.5=0.9v.

Why do we have noise Margin? because the signal will be transmitted at the time of the introduction of noise, at the same time, Ken can be due to the line impedance mismatch and the transmission signal is echoed on the transmit line . The original 4.4V high level, add some chaotic signal, may even 3.5V are not, so there is a logic error.

Moreover, the lower the logic, the higher the likelihood of this error occurring. Because it does not have a large enough noise Margin, 0.8V of Reflection (or Nois) can have little effect on 5V CMOS, but the 2.5 V CMOS is a deadly blow.

2, Loading&fan out

Some output and several other input connections, these are the output of the loading, and the usual load.

The ability to drive input or other types of load per output is limited, and this limit is called its fan-out, and multi-translation is fan-out.

①CMOS Type input, in terms of the output that drives it, mainly shows its capacitive , that is, for output, it can be equivalent to a capacitor that is grounded at the other end of the load. Moreover, the process of level-high to level-low can be equivalent to the output of the capacitor to charge the process, level low to level high, can be equivalent to the capacitance of the output discharge.

Therefore, when describing a logic gate, there will be more IH and IL, the two quantities of a characterization of high power can supply the "outflow" of current size, another characterization of low-voltage "inflow" current size.

When the load exceeds the drive capacity of output, the transmission rate will be greatly reduced because of the reason for charging more "capacitors".

The ②ttl type of I/O is actually connected by a resistor to VCC or GND, similar to the following:

Therefore , in the TTL type circuit, the output low normal settling current (? current-sinking capability) is the most important factor limiting its drive capability.

3. OD door and OC Door

OD Gate full name is open Drain gates, is for the CMOS Gate (Drain), the OC Door full name is open Collector gates is for the TTL of the Collector (Collector).

Using OD doors or oc doors, you need to add a pull resistor to VCC

4, the handling of the suspended pin

At TTL logic level, unused pins generally generate logic high, while unused CMOS pins are preferably grounded or connected to VCC.

Integrated Circuit Intro