Intel System Programming Guide Chapter 1-11th memory type range register (mtrr)

The following sections only apply to P6 and the updated Processor family.

 

The memory range register (Note: plural) provides a mechanism for associating the memory type (see section 11.3) with the physical address range in the system memory. They allow processors to optimize operations for Different Storage types, such as Ram, Rom, frame cache memory, and memory ing I/O devices. They also simplify system hardware design by eliminating memory control pins used for this feature on past IA-32 processors and on the external logic that needs to drive them.

 

The mtrr mechanism allows up to 96 memory ranges to be defined in physical memory, and it defines a set of model-specific registers (MSR) used to specify the type of memory contained in each range. Table 11-8 shows the memory types and attributes that can be specified. Figure 11-4 shows the ing of physical memory with mtrr. See section 11.3.

 

After a hardware reset, P6 and the updated Processor family disable all fixed and variable mtrr, which effectively makes all physical memory unavailable. The initialization software should then set mtrr to a specified memory ing defined by the system. Generally, BIOS (Basic Input/Output System) software is used to configure mtrr. The operating system or advanced execution program can then freely use the page-level cache attribute to modify the memory ing.

In a multi-processor system that uses a P6 family or a newer family of processors, each processorRequiredUse the same mtrr memory ing so that the software has a consistent view of the memory.

Note: In a multi-processor system, the operating system must maintain mtrr consistency among all processors in the system (that is, all processors must use the same mtrr value ). P6 and the updated Processor family do not provide hardware support to maintain this consistency.

 

11.11.1 mtrr feature identification

 

The availability of mtrr features is model-specific. The software can determine whether mtrr is supported on a single processor by executing the cpuid command and the status of the mtrr flag (bit 12) in the feature information register (EDX.

If the mtrr flag is set to 1 (indication, the processor implements mtrr), additional information about mtrr can be obtained from the 64-bit ia32_mtrrcap MSR (which becomes mtrrcap MSR in the P6 family processor. Ia32_mtrrcap MSR is a read-only MSR and can only be read using the rdmsr command. Figure 11-5 shows the content of ia32_mtrrcap MSR. The register flag and domain functions are as follows:

1,Vcnt (number of registers in a variable range) field, ranging from 0 to 7-- Indicates the number of variable range registers implemented on this processor.

2,Fix (supported by fixed range registers) Flag, 8 bits-- When 1 is set, mtrr (from ia32_mtrr_fix64k_00000 to ia32_mtrr_fix4k_0f8000) is supported; When 0 is set, no fixed range register is supported.

3,WC (write binding) Flag, BITs 10-- When set to 1, the write binding (WC) memory type is supported; when the value is 0, the WC type is not supported.

4,Smrr (system management range register) Flag, bit 11-- When bit 11 is set to 1, the system management range register (smrr) interface is supported. When bit 11 is set to 0, smrr is not supported.

 

Ia32_mtrrcap MSR bits 9 and bits 11 to 63 are retained. If the software attempts to write ia32_mtrrcap MSR, a general protection exception (# GP) will be generated.

The software must read the ia32_mtrrcap vcnt field to determine the number of variable mtrr and query other feature bits in ia32_mtrrcap to determine other capabilities supported by one processor. For example, some processors report a value of '8' in the vcnt field, while other Processors may report different values.

 

11.11.2 use mtrr to set the memory range

 

The memory type and memory range specified in each memory range register are set by three sets of registers: ia32_mtrr_def_type MSR, fixed range mtrr, and variable range mtrr. These registers can be read and written using the rdmsr and wrmsr commands respectively. Ia32_mtrrcap MSR indicates the availability of these registers on the processor (see section 11.11.1 ).

 

11.11.2.1 ia32_mtrr_def_type MSR

 

Ia32_mtrr_def_type MSR (mtrrdeftype MSR named as P6 family processor) sets the default attribute of the physical storage area not surrounded by mtrr. The functions of the flag and field in this register are as follows:

1,Type field, ranging from 0 to 7-- Indicates the default memory type used for the range of physical memory addresses that are not specified by a mtrr (see table 11-8 ). The valid values of this field are 0, 1, 4, 5, and 6. All other values will result in a general protection exception (# GP.

Intel recommends that the UC (not cached) storage type be used for all physical memory addresses that do not exist in the memory. To assign values to non-existing memory locations of the UC type, either be specified as the default type in the Type field, or explicitly assign values to fixed and variable mtrr values.

2,Fe (fixed mtrr allowed) Flag, BITs 10-- When 1 is set, mtrr in the fixed range is allowed; When 0 is cleared, mtrr in the fixed range is disabled. When a fixed range of mtrr is allowed and overlapping occurs in the range, they obtain priority to cover a variable range of mtrr. If a fixed range of mtrr is disabled, the variable range mtrr can still be used and can be mapped to a range typically covered by a fixed range of mtrr.

3,E (mtrr allowed) Flag, digit 11-- Mtrr is allowed when 1 is set; When 0 is cleared, all mtrr is disabled and the UC memory type is applied to all physical storages. When this flag is set to 1, the Fe flag can disable the fixed range of mtrr; when this flag is cleared to 0, the Fe flag has no effect. When this E sign is set to 1, the type specified in the default memory type field is used in the memory region that has not been mapped by a fixed or variable mtrr.

The bits 8, 9, and 12 to 63 in ia32_mtrr_def_type MSR are retained; the processor generates a general protection exception (# GP) if the software attempts to write a non-zero value to them.

 

11.11.2.2 fixed range mtrr

 

Fixed memory range is mapped with 11 fixed range registers (each 64-bit. Each of these registers is divided into eight-bit fields, which are used to specify the memory type of each sub-range controlled by the register:

1,RegisterIa32_mtrr_fix64k_00000-- Ing the address range of Kb from 0 h to 7 ffffh. This range is divided into eight 64 kB sub-ranges.

2,RegisterIa32_mtrr_fix16k_80000And registersIa32_mtrr_fix16k_a0000-- Ing two kb address ranges, from H to bffffh. This range is divided into 16 KB sub-ranges, each register has 8 ranges.

3,RegisterIa32_mtrr_fix4k_c0000ToIa32_mtrr_fix4k_f8000-- Ing the address range of eight 32 K bytes, from c0000h to fffffh. This range is divided into 64 4 K byte sub-ranges, and each register has 8 ranges.

Table 11-9 shows the relationship between the fixed physical address range and the corresponding mtrr domain. Table 11-8 shows the memory type encoding of mtrr.

 

11.11.2.3 variable range mtrr

 

The Pentium 4, Intel Xeon, and P6 family processors allow software to specify the memory type for m variable-size address ranges, each range using a pair of mtrr. The number of supported ranges m is given in the bits of ia32_mtrrcap MSR (see section 11-5, 11.11.1 ).

The first entry in each pair (ia32_mtrr_physbasen) defines the storage type of the base address and range. The second entry (ia32_mtrr_physmaskn) contains a mask used to determine the address range. The suffix "N" ranges from M-1 and identifies a specific register pair.

For P6 family processors, the prefixes of these variable ranges of mtrr are mtrrphysbase and mtrrphysmask.

Figure 11-7 shows the signs and fields in these registers. The functions of these flags and domains are:

1,Type field, ranging from 0 to 7-- Specify the memory type for the range (see table 11-8)

2,Physbase domain, 12-bit (MAXPHYADDR-1)-- Specify the base address of the address range. When maxphyaddr is 36 bits, 12 bits are extended at the low end to form the base address (which is automatically aligned with the address on a 4 K byte boundary ).

3,Physmas domain, 12-bit (MAXPHYADDR-1)-- Specify a mask (if the maximum physical address is 36 bits, it is 24 bits; if the maximum physical address is 40 bits, It is 28 BITs ). The mask determines the range of the region to be mapped based on the following relationships:

-- Address_within_range: 'physmask = physbase 'and 'physmask

-- This value is extended to 12 bits at the low end to form the mask value.

-- The width of physmask depends on the maximum physical address size supported by the processor.

The maximum physical address size supported by the processor is 8 hours. If cpuid.8002138h is unavailable for 8 hours, the software must assume that the processor supports a 36-bit physical address size (physmask is 24-bit wide, and the 28-bit height of ia32_mtrr_physmaskn is retained ).

4,V (valid) Flag, digit 11-- When 1 is set, register pairs are allowed. When 0 is cleared, register pairs are prohibited.

Ia32_mtrr_physbaseNAnd ia32_mtrr_physmaskNAll other bits in are retained; if the software attempts to write to them, the processor generates a general protection exception.

Some mask values may cause discontinuous ranges. In this range, the areas not mapped by the mask value are set to the default memory type. Intel does not encourage the use of "discontinuous" ranges because they may require memory to exist through the entire 4 GB physical memory ing. If the storage is not provided, the action is undefined.

 

Note: For software, it is possible to use the ACPI/int15 e820 interface mechanism to parse the memory description provided by BIOS. This information can then be used to determine how mtrr is initialized (for example, to allow the BIOS to define the Effective Memory range supported by the platform, including the processor, and the maximum memory range ).

See section 11.11.4.1.

 

11.11.2.4 system management range register Interface

 

If ia32_mtrrcap [bit 11] is set to 1, the processor supports the smrr interface to restrict a specified SMM) access to the memory address range used by the software (see section 26.4.2.1 ). If the smrr interface is supported, The SMM software is strongly encouraged to use it to protect the SMI code and data stored by the SMI processing routines in the smram region.

The system management range Register consists of a pair of MSR (see Figure 11-8 ). Ia32_smrr_physbase MSR defines the base address of the smram memory range and the type of memory used to access the smram memory range in SMM. Ia32_smrr_physmask MSR contains a valid bit and a mask that determines the smram address range protected by the smrr interface. These MSR can only be written under SMM; an attempt to write them outside SMM will lead to a general protection exception.

 

Figure 11-8 shows the signs and fields in these registers. The functions of these flags and domains are as follows:

1,Type field, ranging from 0 to 7-- Specifies the memory type of the range.

2,PhysbaseDomain, ranging from 12 to 31-- Specifies the base address of the address range. The address must be smaller than 4G bytes and be automatically aligned on a 4 kb boundary.

3,PhysmaskDomain, ranging from 12 to 31-- Specifies a mask that determines the range of the region to be mapped. Based on the following relationship:

-- Address in the range and physmask = physbase and physmask

-- This value is extended to 12 bits at the low end to form the mask value. For more information, see section 11.11.3.

4,V (valid) Flag, digit 11-- When 1 is set, register pairs are allowed; When 0 is cleared, register pairs are prohibited.

 

Before attempting to access these smrr registers, the software must test the bit 11 in the ia32_mtrrcap register. If smrr is not supported, reading and writing these registers will cause general protection exceptions.

When the valid identifier of ia32_smrr_physmask MSR is 1, access to the specified address range is treated as follows:

1. If the logic processor is in SMM, access the memory type in ia32_smrr_physbase MSR.

2. If the logic processor is not in SMM, write access is ignored, and read access returns a fixed value for each byte. The memory type (UC) that cannot be cached is used in this case.

 

Even if the specified address range overlaps with a range specified by mtrr, the above terms are applied.

 

11.11.3 example: Base and mask computing

 

The example in this section applies to a processor that supports a 36-bit maximum physical address size. The base and mask values that enter the variable range mtrr are 24 bits, which are extended from the processor to 36 bits.

For example, if the base address in the ia32_mtrr_physbase3 register is 2 MB (00200000 H), the 12-bit minimum valid bit is truncated and the value of H is input to the physbase domain. The same operation must be performed on the mask value. For example, if the ing address ranges from H to 3 fffffh (2 MB to 4 MB), a mask value fffe00000h is required. Again, the minimum valid bit of the mask value is truncated. In this way, the value entered in the physmask field of ia32_mtrr_physmask3 is fffe00h. This mask is selected so that any address in the range from 200000h to 3fffffh is 'and' with the mask value (200000 H '.

To map an address range from H to 7 fffffh (4 MB to 8 Mb), a base value of H is input to the physbase domain, and a mask value fffc00h is input to the physmask domain.

 

11.11.4 range size and alignment requirements

 

A range of mtrr to be mapped to a variable range must meet the following "2 power" size and alignment rules:

1. The minimum range is 4 kb, and the base address of the range must be aligned at the boundary of at least 4 kb.

2. For a range greater than 4 kb, each range must be 2n in length and its base address must be aligned at a 2n boundary, while N is a value greater than or equal to 12. The base address alignment value cannot be smaller than its length. For example, an 8 KB range cannot be aligned at a 4 kb boundary. It must be aligned at least one 8 KB boundary.

 

11.11.4.1 mtrr priority

 

If mtrr is not allowed (by setting the E flag in ia32_mtrr_def_type MSR), all memory accesses are of the UC memory type. If mtrr is permitted, the type of memory used for one memory access is determined by the following conditions:

1. If the physical address falls within the first 1 MB of the physical memory and the fixed mtrr is allowed, the processor uses the memory type suitable for the fixed range of mtrr.

2. Otherwise, the processor tries to match the physical address with a memory type set by a variable range of mtrr:

-- If a variable memory range matches, the processor uses the memory type stored in the ia32_mtrr_physbasen register for that range.

-- If two or more variable memory ranges match and the memory type is the same, the memory type is used.

-- If two or more variable memory ranges match and one of the memory types is UC, the UC memory type is used.

-- If two or more variable memory ranges match and the storage type is wt and WB, The wt storage type is used.

-- For the stacked transactions that are not defined in the above rules, the processor's behavior is undefined.

3. If there is no variable or fixed memory range match, the processor uses the default memory type.

 

 

11.11.5 mtrr Initialization