interface and program in SV

The newly defined interface in INTERFACE:SV is used to simplify the interface connection, and when used, the Interface is defined outside the module or program and then added to the project through the ' include '.

Interface arb_if (input bit CLK); CLK signal, usually taken out separately

Logic [1:0]grant, request; Only the signal type is defined. The types are defined separately in different modport.

Logic rst;

Clocking CB @ (Posedge CLK); Defines the clock block, where the signal is valid for the CLK rising edge

Output request;

Input Grant;

Enclocking

Modport TEST (clocking CB, output RST); Direct reference to clocking, in defining the orientation of the RST

Modport DUT (Input request, RST, output grant); Define the direction of each signal

Endinterface

Module Test (arb_if. TEST arbif);

Initial begin

Arbif.cb.request <= 0; The signal in the clocking is directly referenced, and the signal in the interface can only use <= non-blocking assignment.

@arbif. CB; Equivalent to @posedge CLK

$display ("");

End

Endmodule

The interface can be connected directly to the VERILOG-2001 port:

Module top;

Bit CLK;

Always #5 CLK = ~CLK;

Arb_if arbif (CLK);

Arb_port A1 (. Grant (Arbif,grant),

. Request (Arbif.request),

. RST (Arbif.rst),

. CLK (ARBIF.CLK));

Test T1 (ARBIF);

Endmodule:top

Program: The main purpose is to distinguish between RTL and verification platform in logic and simulation time. In an SV-built validation environment, TestCase typically defines a program to begin execution.

Always is not available in program because the program is closer to the C language compared to the other. So you can use more initial. The simulation time in program is different from that in RTL,

SV divides the same simulation time into four zones, Active (design), observed (assertion), reactive (testbench), postponed (sample). Equivalent to the base of the original Verilog

An execution interval, a sampling interval, is added to the program. So the definition of CLK cannot be placed in program. When the initial in program finishes, the SV invokes $finish to complete the simulation.

interface and program in SV