Interrupt-PIC-APIC

Interrupt (interrupted)

1. Concept

The so-called interruption refers to the process in which the CPU forces the CPU to stop the program currently being executed due to an external or internal event, the service is switched to the Event Service (called the interrupted service). After the service ends, the service can be automatically returned to the interrupted program for further execution.

2. Background

Interruption is an important technology in computer development. Its appearance has largely liberated the CPU and improved the execution efficiency of the CPU. Before the interruption occurs, the CPU uses the polling method for the IO service, which makes the CPU tangle on a certain Io and waits for its response. If it does not respond, the CPU keeps waiting. In this way, other IO ports are waiting for the CPU service. If an IO has important or emergency affairs, the CPU will not be able to respond to this Io. To solve this tangled problem, ------> there was an interruption.

The main advantage of interrupt control is that it responds only when the I/O interface needs services, so that the CPU can do its own thing calmly, only when the IO port is required can it be responded. At the same time, the interrupt priority is also designed to handle some urgent events.

3. Category

The relationship between the CPU and the interrupt source (the device and the event that can initiate the interrupt request are called the interrupt source) can be divided into internal interruption and external interruption.

1) Internal interruption: it is also called an abnormal interrupt. It is an unshielded interrupt, which is an interruption caused by the processor's detection of exceptions or the execution of software interrupt commands. Generally, there are Division Error interruptions (int0), breakpoint interruptions (int3), overflow interruptions (int4), and single-step execution interruptions (int1. Exceptions are divided into faults and traps.

2) External Interrupt: Also known as hardware interrupt. It is an interrupt triggered by external CPU pins, including unshielded interrupt NMI (int2) and shielded interrupt Intr.

4. Priority Level of the interrupt source

The maximum number of internal interruptions (except for one-step interruption) is NMI interruption, and intr interruption again. The execution interruption in one step is the lowest.

5. interrupted vector table

In real address mode, the CPU uses the space from 0 to 1 kb in the memory as an interrupt vector table.

The interrupt vector table is a chain table between the interrupt type number and the interrupt service program entry address.

The system divides the interrupt source into 256 types. The type number ranges from 0 ~ 255 (0 ~ FFH. Each interrupt type is allocated with four consecutive byte units, which are used to store the entry address of the interrupt service program and the base address of the two high byte units, the offset address of the entry for storing two low-byte units. Therefore, the 256 interrupt vectors occupy the system's lowest 1 kb memory.

The interrupt type number N corresponds to the interrupt service program entry address 4N, that is, the entry offset address is stored in the storage unit indicated by 4N and 4n + 1, the base address of the entry is stored in the storage unit indicated by 4n + 2 and 4n + 3.

Interrupt type no. 0 ~ 31 is reserved by the CPU, 32 ~ The value 255 is user defined.

6. Interrupt Descriptor Table

In protection mode, the interrupt vector table consisting of four bytes cannot meet the requirements. In protection mode, the table items in the interrupt vector table are composed of 8 bytes. At this time, he also has a new name ----> interrupt description table (Interrupt Descriptor Table, IDT), where each table item is called a gate descriptor ).

Door type characters are mainly divided

A. Interrupt gate (Interrupt gate): The type code is 110. The interrupt gate contains the separator and intra-segment offset of the segment where the interrupt or exception handling program is located.

When the control enters the interrupt processing program through the interrupt door, the processor clears the if sign, that is, the disconnection is achieved, thus avoiding the interruption nesting.

The DPL (request privilege level) in the interrupt gate is 0, so the process in the user State cannot access the interrupt gate. All the interrupt handlers used are activated by the interrupt gate and are limited to the kernel state.

B. the type code of the trap gate (TAP gate) is 111. Similar to the interrupt gate, the only difference is that the if flag remains unchanged when the control enters the processing program through the trap gate, that is, the interruption is not disabled.

C. System Gate: the Linux kernel is specially set to allow user-State processes to access Intel's trap gate.

The dpl of the system door is 3. A system call enters the kernel through the system gate.

In protection mode, the position of the Interrupt Descriptor Table in the memory is no longer limited to the starting position from address 0, but can be placed in any location in the memory.

1> to implement this function ---> An Interrupt Descriptor Table register idtr is designed in the CPU to store the Interrupt Descriptor Table at the starting position of the memory.

2> the interrupt description table register is a 48-bit register. Its Low 16 is to save the size of the Interrupt Descriptor Table, and the high 32-bit stores the base address of the interrupt description table.

7. interrupt handling process

Four processes of Interrupt Processing: interrupt application, interrupt response, interrupt processing, and interrupt return.

1) interrupt Application

When an external device needs to interrupt the service, a hardware interrupt request signal int is sent to the CPU, and the int signal is required to be kept until the CPU responds.

2) interrupt response

After each command is executed, the CPU queries whether there are any interrupt requests. If an interrupted request is found and response interruption is allowed, the system automatically enters the interrupted response cycle, the hardware completes a series of operations such as disconnection, resumable storage, and the entry address of the disconnected service program, and then switches to the interrupted service program to execute the interrupt processing.

3) interrupt handling

Interrupt handling is the operation specified in the interrupt service program. Before that, we usually do two things:

Protection site: Use the push command to import the content of the relevant register into the stack,

Open interrupt: aims to implement interrupt nesting. Use the instruction STI.

4) return of Interruption

It is completed by the instruction iret returned by the interruption. Before that, use the pop command to restore the stored field information.

PIC

1. Concept

The programmable interrupt control (PIC) programmable interrupt controller is generally an interrupt control system consisting of two intel8259a cascade units that support up to 15 interrupt vectors. Each 8259a can process up to 8 different IRQ. Since the int output line of the PIC is connected to the irq2 pin of the main pic, the number of available IRQ lines reaches 15

2. 8259a Principle

1) 8259a Structure Diagram

2) Three Important interrupt status registers

IRR (interrupt request register) interrupt request register.

ISR (interrupt service register) interrupt service register.

IMR (Interrupt Mask register) Interrupt Mask register.

3) working method of 8259a

4) cascade of 8259a

5) 8259a Programming

There are two working modes: programming mode and operation mode;

Two types of command words are supported: the initialization command word (ICW) and the Operation Command word (OCW ).

6) 8259a initialization process

During BIOS initialization, the initialization command ICW is written to the IO port to program 8259a. After that, 8259a can respond to interrupt requests from external devices.

The IO address of Aster is 0x20, 0x21, irq0 ~ Irq7: the interrupt vector number is 0x08 ~ 0x0f (legacy mode)/0x68 ~ 0x6f (protected mode ).

The IO address of slave is 0xa0, 0xa1, irq8 ~ Irq15, the interrupt vector number is 0x70 ~ 0x77

Icw1 format:

Icw2 format:

Icw3 format:

Main film:

Slave slice:

Icw4 format:

7) 8259a Operation Mode

Interrupt operation programming refers to writing the OCW command word at any time during the 8259a operation to read the status or make 8259a work according to the new setting.

Ocw1:

Ocw2 is used to set the interrupt priority mode and interrupt end mode:

Ocw3 is used to set or clear the special shielding mode and read the register status.

8) processor Interface

-CS A0-rd-WR Function

0 0 1 0 write icw1, ocw2, ocw3

0 1 1 0 write icw2, icw3, icw4, ocw1

0 0 0 1 read IRR, ISR, and query words

0 1 0 1 read IMR

0x1 1 high-impedance data bus status

1 x high-impedance data bus status

APIC

1. Concept

APIC (advanced programmable interrupt control) advanced programmable interrupt controller.

It consists of two parts:

Io APIC: located in the south bridge, used to handle various interruptions caused by devices on the bridge. It is used to receive the interruption from the IO Device and send it to the local APIC. There are usually 24 inputs.

Local APIC: It is located in the CPU, and each CPU has one. Transfers an interruption to a specified processor.

2. Differences between APIC and PIC:

1) Like pic, the method for controlling local APIC and io apic is also to read and write the relevant registers in this unit. The difference is that Intel registers in the local APIC and io apic are mapped to the physical address space:

The local APIC is mapped to the physical address 0xfee0 0000 by default.

Io APIC is mapped to the physical address 0xfec0 0000 by default.

2) Unlike the 8259a IRQ pin, the interrupt priority has nothing to do with the position of the interrupt input signal. On the contrary, software can determine the interrupt vector, interrupt priority, shielding bit, triggering method, polarity of the interrupt pin, transmission mode, transmission status, and destination of each interrupt input pin, and each one can be set separately.

3. Io APIC

1) The chip implementing Io APIC is 82093a.

2) Io APIC function:

The IO Device must send an interrupt request by triggering the interrupt line (intin0 ~ Intin23), Io APIC uses the corresponding information in the redirection table entry to format an interrupt request and send it to the local APIC.

3) Important register in Io APIC:

4. Local APIC

1) it exists in the CPU, and several CPUs have several local APIC.

2) two major functions of local APIC:

One is to receive the interruptions from the CPU interrupt pin, internal interrupt source, external Io APIC, and send them to the processor core for processing.

The second is to send and accept IPI messages (Inter-processor interrupt) from other processors on the system bus in a multi-processor system (MP ).

3) Each local APIC consists of a set of APIC registers and hardware that sends interrupts to the processor core and generates IPI messages. APIC registers are memory ing and can be read and written using mov commands.

4) The local APIC can receive the following interruptions from the interrupt source:

A. External Interrupt Device

These Io devices connect to the intin pin of the io apic, And the interrupt request information is transmitted to the local APIC through the io apic.

B. interruption between processors (IPI)

Processor triggers IPI by writing the interface (Interrupt command register.

C. Local interrupt source, which includes five types

1> Local I/O device

These Io devices are connected to the processor's local interrupt pin (lint0/lint1) or can also be connected to the 8259 interrupt controller, 8259 and lint0/lint1.

2> APIC timer interrupt (APIC timer interrupted)

3> Performance Monitor counter interrupt (performance monitoring counter interrupted)

4> thermal sensor interrupt (temperature sensor interrupted)

5> APIC internal error interrupt (APIC internal error interruption)

After the local APIC receives the interruptions from these five types of local interrupt sources, the local vector table (lvt) the configured interrupt delivery protocol sends the interrupt information to processor core.

Address: 0xfee00330 ~ 0xfee00370

5) how to determine whether a local APIC exists or not?

MoV eax, 1

Cpuid

If edX bit9 = 1 is returned, it exists; If bit9 = 0, it does not exist.

6) How to enable/disable local APIC?

Two methods:

1. APIC global enable/disable flag in MSR ia32_apic_base

2. APIC software enable/disable flag in 0xfee0 00f0

Difference: After global disable, the local APIC can be re-enabled only after one power up or reset.

Software enable/disable can be set only when global enable is enabled.

5. APIC architecture version

1> APIC

Pentium/P6 series CPU usage, local APIC and io apic communicate through the APIC bus.

2> xapic

The pentium4/Xeon series CPU is used. Local APIC and io apic communicate with each other through system bus. xapic is an extension or modification of some features in the APIC architecture.

3> x2apic

Is the extension of xapic, mainly the extension of processor addressability.