Interrupt processing of "assembly language" ARM processor

Interrupt handling of ARM processors

1) There are 8 operating modes in the arm processor (and the CPU handles different task modes), typically 5 Abnormal mode, In these 5 Modes There are three interrupt mechanisms, namely the FIQ mode (High priority interrupt mode);IRQ Mode (Low-priority interrupt mode), and one that is the SVC mode (the mode generated when the reset or soft interrupt (SWI) instruction executes)

2) First understand what the interrupt mechanism is

In bare-metal arm ,theSOC supports hardware interrupts (interrupt controllers), so how interrupts are generated when the CPU Processor is executing an instruction, Sudden interruption of external interrupt request or internal interrupt signal (interrupt signal source)

3) becauseArmthe processor supports hardware interrupts, forFIQand theIRQinterrupted, inArmThe kernel will lead to two lines of disconnection, whenCPUafter each instruction is executed, the interrupt request input line is automatically detected to determine if there is an externally sent interrupt request signal. Since interrupts are shielded, the generalArmThe interrupt is initially masked, i.e.IFto be1.in fact, here the interrupt request register is not directly connected to theIRinterrupt line, but to distinguish between the interrupt controller and determine the priority of multiple interrupt requests at a certain time, eventually through the interrupt controller (control comparator) to transmit the transmission interrupt request, and the processor will also pause the instruction being decoded, the pointer jumps to the corresponding exception vector table. In theRAMbare Metal without an operating system, when entering the exception handler is, in memory we should establish maintenance of an exception vector table, initialize the stack of space in order to jump running space, in addition to do an important thing, that is to save the scene and after the exception of the site recovery, here throughArmThe pipelining of executing instructions discovers that when an interrupt is entered, the processor pauses the instruction being decoded, ① at this time, we should save theLRthe address value of the register minus4after savingSub LR, LR, #4 stmfd sp!, {r0-r12, LR};

③ at the time of the stack, as long as the resumption of the scene can be, the general operation Ldmfd Sp!, {r0-r12, pc}^ @ when the stack and restore CPSR

② in fact, after the protection of the scene, we have to do is how to deal with the corresponding interrupt exception, in the assembly can be done by the B Do_irq_func jump C function to write the processing function.

4) The interrupt request register is a register connected to the interrupt request line of the external interface, and the interrupt-requesting peripheral requests the interrupt service to the interrupt controller via ir0~ IR7 , and keeps the state of the interrupt request in the interrupt request register at arm There are 3 Interrupt Request registers in the processor processing 94 Interrupt Request, when the external interrupt request, will be through the corresponding logic circuit level will be changed, Here the interrupt excitation mode has rising edge, falling edge, double edge, high level and low level,

External interrupt Management module with 32 pins drawn from the SOC,
These pins are multiplexed, can be configured as general-purpose input/output IO, or can be configured as
Wake-up interrupt mode (and internal connection to the interrupt Controller circuit). The GPIO module is internally
Three registers manage the interrupt function for these 32 pipelines.

GPH0. Gph0con = GPH0. Gph0con & ~ (0xf << 8) | (0x2 << 8);

Here, the key's key is set to the middle Wake Interrupt control mode by the pin of the GPIO universal output input interface, so that the interrupt mechanism can be realized by pressing the key.

(1) Function register, to manage the level excitation mode of the pin, can be equipped with
High level excitation interrupt, low level, rising edge, falling edge, double edge, etc.

Wu_int0_7_con = Wu_int0_7_con & ~ (0x7 << 8) | (0x2 << 4);

(2) Mask Register External pins EINT16 to EINT31 a total of 16 wires shared one
The root line Eint (16-31) is connected to the interrupt controller, which is a common interrupt number (interrupt
Number 16), it may be necessary to have only one pin line signal at a time through the module
To the interrupt controller, this time the rest of the pin signal must be shielded, such as
What about He Shi? is to set the corresponding bit in the mask.

Wu_int0_7_mask = Wu_int0_7_mask & ~ (1 << 2);

Setting the Mask register allows the interrupt to enter when an interrupt is triggered, because the processor can only handle a single interrupt at a specific time

(3) Pend Register record interrupt signal flag. If the signal passes through the front
The corresponding bit value of the Pend register on the corresponding line is 1, if
At some point, the interrupt controller cannot handle the interrupt request on the current signal line, then
The Pend bit will keep this request, even if the interrupt excitation state on the hardware interrupt line
Is over. Again, it is important to note that if the current interrupt on the line has been processed, the
The Pend bit is not automatically zeroed out and requires artificial zeroing.

(4) When the previous preparation work is completed, we should also do important things, that is, the interrupt controller to open the corresponding interrupt source switch, the interrupt request signal can be interrupted by the interrupt controller from the corresponding IRQ or FIQ to trigger the processor to perform the interrupt, The interrupt controller here also does an important thing is to register the corresponding interrupt processing function to the address register, then the ARM processor can default by pointing to address to implement the interrupt function, then how to handle the function by an address, It involves the concept of a function pointer referring to the address (where the function name of a function is the entry address of the function) to invoke the interrupt function.   form void (* Pfunc) (void);  Pfunc = (void *) address; ;p func ();

3) What is an IRQ interrupt

The full name of the IRQ is "Interupt request", or "Interrupt request". When the peripheral hardware inside the computer needs the processor to perform some work, the hardware sends a hardware signal that notifies the processor that the signal is an IRQ. Why is it called "interruption"? "Interruption" means that even if the processor is doing other work, when it receives the interrupt signal from the peripheral device, the processor will stop, prioritize the work of the signal, and then proceed with the unfinished work before proceeding.

4) What is IRQ conflict

The number of IRQ is limited, although a computer has a total of 16 IRQ (from IRQ0 to IRQ15), but many of them are pre-assigned to specific hardware, as follows: IRQ0: System timer IRQ1: Keyboard IRQ2: Interrupt control card can be set IRQ3:COM2 (Serial Interface 2) IRQ4:COM1 (serial interface 1) IRQ5: Not preconfigured IRQ6: disk drive IRQ7: Parallel interface irq8:cmos/clock IRQ9: Not preconfigured IRQ10: not preconfigured IRQ11: not preconfigured irq12:p S/2 Mouse IRQ13: Arithmetic processor (arithmetic Processor) irq14:primary (primary) IDE controller irq15:secondary (from) IDE controller visible from above, IRQ5, IRQ9, IRQ10 and IRQ11 are vacant. But let's not assume that this means there is an extra IRQ to use. Because there are too many peripherals to use IRQ, such as a PCI or ISA device such as a sound card or network card, you need to configure an IRQ. If there are two devices configured with the same IRQ, there will be an IRQ conflict problem, so that both do not work properly.

5) What happens if I encounter an IRQ conflict

Motherboard has four or more PCI slots.   If all the PCI expansion cards are plugged in, how can the four vacant IRQ be enough? In fact, some hardware can be used to share an IRQ, and some are not. For example, a PCI sound card needs to have an IRQ on its own, sometimes even two, one for MIDI (a flute) and one for wave (wave table). Therefore, when the system automatically assigns IRQ, if the sound card is assigned to share an IRQ with other devices, the likelihood of an IRQ conflict is very high, and the solution is to manually assign the IRQ, set in the BIOS.

6) Soft Interrupt

Programming exceptions are often called soft interrupts

A soft interrupt is a signal communication method used to simulate a hard interrupt between communication processes.

After interruption of the source interrupt request or soft interrupt signal, the CPU or receiving process automatically interrupt processing at the appropriate time or complete the soft interrupt signal corresponding function soft interrupt is the software implementation of the interruption, that is, the program is run by other programs interrupt it, and the hard interrupt is the hardware implementation of the interruption of the device when the program runs.

1. The time the soft interrupt occurs is controlled by the program, and the time that the hard interrupt occurs is random

2. Soft interrupts are caused by a program call, and a hard interrupt is triggered by a peripheral

3. Hardware interrupt handler to ensure that it can complete its tasks quickly so that the program executes without waiting for a longer time

SWI: Software Interrupt

(Soft ware Interrupt)

swi{conditions} <24 bit number >

Instruction format This is a simple facility, but may be the most commonly used. Most of the operating system facilities are provided with SWI. The RISC OS without SWI is unthinkable.

Interrupt processing of "assembly language" ARM processor