Interruption system design of μC/OS-ⅱ on the X Platform

Interruption system design of μC/OS-Ⅱ on the X Platform

[Date: May 10,

Source: single-chip microcomputer and Embedded System Application Author: Bai Fenge, Taiyuan University of Technology Chen Yanbin

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Introduction
The embedded real-time system requires the system to have good real-time performance and be able to handle various abnormal events in a timely manner. Therefore, the interrupt system is an important part of the embedded real-time system, its Time and Space performance is crucial to the performance of embedded real-time systems. To shorten the interrupt response time of an embedded real-time system and improve the efficiency of Interrupt Processing, it is critical to design an interrupt system reasonably. As a microprocessor based on the ARM7TDMI kernel of Samsung,-box supports IRQ and FIQ interrupt requests and vector interrupt to shorten interrupt response time. The embedded real-time operating system μC/OS-II provides a simple interrupt management mechanism for unified management of system interruptions, but does not provide specific Interrupt Processing Methods for different microprocessor. Based on the in-depth analysis of the interrupt control system and the interrupt management mechanism of μC/OS-II, the paper designs the interrupt system to better meet the needs of practical application.

1 Interrupt System
Figure 1 shows the Interrupt System Structure of the box. The task of the interrupt controller is to determine the priority and select one of the interruptions when multiple interruptions are made up of the On-chip peripheral and off-chip interrupt sources; IRQ or FIQ is used to send IRQ or FIQ interrupt requests to the ARM 7 kernel. The ARM 7 kernel obtains the interrupt information from the interrupt controller and then processes the interrupt to control the operation process of the interrupt device.

When the ARM 7 kernel receives an interrupt request from the interrupt controller, it automatically performs the following steps to protect the interrupt environment and redirect the program:
① Save the content of the Program Status Register CPSR to the program status preservation register SPSR In the interrupt mode to be executed, to save the current status of the processor, the interrupt shielding bit, and the flag bit of each condition.
② Set the corresponding bit in the current CPSR to block the corresponding interrupt and switch the processor mode.
③ Save the address (breakpoint address) of the next instruction that causes the interruption to the subroutine link register LR in the interruption mode, so that the interrupted service program can return the original program correctly after execution.
④ Assign a value to the program counter PC so that the program executes the interrupted service program starting from the corresponding vector address.
After the interrupted service program is executed, perform the following steps to return from the interrupted service program:
① Recover all modified General registers from the interrupt mode stack (RO ~ R12 ).
② Copy the content of the SPSR register in the interrupt mode to the CPSR to restore the working state of the program in the interrupt mode.
③ Assign the LR content to the PC so that the PC returns the result to the corresponding instruction.
④ Clear the mark of interruption prohibition in CPSR.
During the process of return from the interruption, ② and ③ must be completed at the same time.

2 μc/OS-II interrupt handling process
The μ C/OS-II provides functions OSIntEnter () and OSIntExit () for interrupt processing. The OSIntEnter () function notifies the operating system of the interrupted service program. The OSIntExit () function performs corresponding processing when the interrupted service program returns. The interruption response process 2 of the μC/OS-II is shown. When you enter the interrupt service program, first save all the CPU registers to the current task stack, then call the OSIntEnter () function, or add the interrupt nested layer counter, that is, the global variable OSIntNesting directly to 1, notifies the μC/OS-II to enter the interrupt service program and executes the user code to interrupt the service. Call the OSIntExit () function after the service interruption is completed to change the variable
OSIntNesting minus 1. When OSIntNesting is reduced to O, all interrupted executions are completed, and the μC/OS-II wants to determine if there is a higher priority task that is awakened by the interrupted service program. If a high-priority task enters the ready state, the μC/OS-II returns to the high-priority task for execution; otherwise, returns to the current task for continued execution.

Through the analysis of μC/OS-II interrupt processing process, we can see that μC/OS-II only provides a simple interrupt management mechanism, no specific solutions are provided for problems such as interrupted Environment Protection During interrupted entry, interrupted environment recovery during interrupted exit, interrupt nested processing, and stack allocation. In addition, for different processors, the broken processing method is not the same, so the transplantation of μC/OS-II on different processors, according to the specific characteristics of the processor, design the Interrupt System.

3. Interrupt System Design
During the design of the interrupt system, all IRQ interruptions are included in the management scope of the operating system, which is centrally managed by the operating system. FIQ interruptions are independent of the operating system and are not managed by the operating system. Therefore, the Interrupt System is designed in two parts: IRQ interrupt and FIQ interrupt.
3.1 Interrupt System Structure
Both IRQ and FIQ interrupt modes are provided in the box. FIQ interruptions are designed in ARM to be used for fast processing. However, any interruptions to be managed in the operating system must be prepared and terminated in the later stages, this includes the storage environment for interrupted tasks. If FIQ interruptions are managed by the operating system, the advantage of FIQ interruptions is not obvious. Therefore, FIQ interruptions are not included in the management scope of the operating system during the design process, instead, the user independently designs FIQ service interruption programs.
For IRQ interrupt mode, X provides vector interrupt mode, which can reduce the number of jumps of the interrupt program and shorten the interrupt response time; however, after the μC/OS-II is transplanted to the b0x processor, all IRQ interruptions should be managed by the operating system in a unified manner, that is, when an interruption occurs, the program must jump to a unified entrance to protect the interrupted environment and then execute the interrupted service program. If vector interrupt is used, the interrupt response time cannot be shortened. In the case of interruption, the interrupt response time is extended because the program needs to jump to the unified entrance.
According to the above analysis, FIQ interruptions are not included in the management scope of the operating system, but are designed by the user based on the actual situation. On the one hand, it can provide fast interrupt response, and on the other hand, it enhances the flexibility of the system. At the same time, because vector interrupt is used in the operating system, it cannot speed up the response of interruption, therefore, vector interrupt is not used in the design of the interrupt system. The structure of the interrupt system is shown in 3. When IRQ is interrupted, the processor will take the command from ox18 and execute the jump command at 0x18 to redirect to the unified interrupted population, after interruption distribution and Environmental Protection, execute specific interrupt service programs. The IRQ interrupt handling process is centrally managed by the operating system. Compared with IRQ interrupt, FIQ interrupt processing is relatively simple. When FIQ interrupt occurs, the processor will execute the jump command at address 0x20 and directly go to the specific interrupt service program.

3.2 ARM processor running mode
Arm processors can run in seven modes: user mode (usr), system mode (sys), management mode (SVC), abort mode (ABT), and undefined mode (UND) normal interrupt mode (IRQ) and fast interrupt mode (FIQ ). The processor is in different modes under different circumstances. The design of the interrupt system mainly involves SVC, und, IRQ, and FIQ modes.
In ARM processor, SVC mode is usually the operating system kernel code running mode, the main code in μC/OS-II kernel is run in SVC mode, and the system task code is run in SVC mode.
The IRQ/FIQ mode is the mode in which the processor is forced to enter after an IRQ/FIQ interrupt occurs. It is used for interrupt processing. When IRQ/FIQ is interrupted, the ARM processor automatically changes the LR register in IRQ/FIQ mode, and the LR stores the return address in the interrupted mode (the Pc value before the interruption ), in this way, when the function exits, the system returns to the interrupted mode correctly. LR is also the return address register for function calls in each mode. That is to say, the LR register has two functions: saving function return address and interrupt return address. The two functions of LR conflict with each other in interrupt nested programming.
If you use the IRQ/FIQ mode to nest the interrupt itself, after the LR in this mode is rewritten, the original function return address in this mode cannot be restored. Therefore, the interrupted service program should be switched to SYS mode to run after basic environment protection is performed in IRQ/FIQ mode when interruption is disabled. This processing method ensures that when interrupt Nesting is generated, the interrupted mode is SYS mode rather than IRQ/FIQ mode itself. LR in IRQ/FIQ mode stores the return address in SYS mode, the LR in SYS mode is not damaged, and the return address of the function is saved. Replace SYS mode in UND mode in transplantation as the running mode of the interrupted service, which can implement the nested interrupt function.
3.3 interrupt nesting
Nesting should adopt the semi-nesting mode, and does not require full nesting. "Semi-nesting" means that different device interruptions can be nested, but the same device interruption cannot be nested. This design not only takes care of the real-time requirements of the system, but also makes the system more explicit and stable; otherwise, if the development is completely nested, there will be uncertainty in the stack space for service interruption, there is even uncertainty in the upper limit of interrupt response time, which obviously cannot meet the requirements of embedded real-time systems.
You can set the CPSR register's interrupt shielding bit F/I to block system interruptions. Such protection is called "Hard protection "; A specific interrupt is blocked by setting the corresponding bit in the interrupt shield register. Such protection is called "device protection ". To implement the semi-nested mode, you need to switch between the two protection modes at the right of the interrupt Entry and Exit:
① Exit hard protection when data is not read after the device is protected.
② Resume the hard protection of the system before exiting ISR to enable device interruption.
The specific implementation process is shown in step 4.

3.4 IRQ interrupt Design
IRQ interrupt processing involves the process of interruption environment protection, processor operation mode switching, and interruption environment recovery. The interrupt handling process is as follows:
Interrupt entry condition: IRQ interrupt shielding. LR indicates the PC value in the interrupt mode, SPSR indicates the current processor status value in the interrupt mode, and SP indicates the current stack pointer value in the irq mode.
① Save the environment in IRQ mode.
② Determine whether it is the first-level interruption. If it is not a program jump to ④.
③ Set the OSIntNesting variable to 1 and switch to SVC mode to save the interrupt environment saved in the IRQ mode stack to the task stack, the SP pointer of the current task is saved to the task control block. Switch to the UND mode to run the interrupt service program ISR, and the program jumps to ⑤.
④ Interrupt nested layer variable OSIntNesting plus 1, switch to UND mode, copy the task environment stored in IRQ mode to the ISR stack, that is, the UND mode stack.
⑤ Call the IRQ interrupt handler to execute the interrupt service program.
6. Interrupt termination. Blocks the interrupt and reduces the nested count of the interrupt to determine whether it is the last layer. If not, the service is interrupted. Otherwise, the task is scheduled to run the task with the highest priority.
7. Restore the ISR environment of the last interrupted service program and execute the interrupted service program on the last layer.
The specific process of executing the interrupted service program is shown in step 5.

3.5 FIQ interrupt Design
After the μC/OS-II is transplanted to the 4480x, the μC/OS-II does not manage FIQ interruptions, which can reserve a fast response interruption source for the system. If multiple interrupt sources are configured as FIQ interruptions during the system design process, the interruption is distributed at the interrupt entry and then enters the corresponding interrupt service program. This will increase the response time of the interruption. Therefore, an independent interrupt source should be set for FIQ interruption in the system design. FIQ interrupt procedures need to be independently designed by the user because the μC/OS-II does not manage FIQ. The execution process of FIQ interrupt service program 6 shows that after FIQ is interrupted, the system enters the FIQ mode to perform simple environment protection, then executes the interrupt service program, and finally restores the interrupted environment and returns. All these tasks are completed in FIQ mode.

4. System Testing
The system test environment is hf44b0a developed by Beijing Hengfeng ruike Company, and the Development Board is also available in v2.61 of μC/OS-II. The system test includes three parts: the timer interrupt test, the IRQ Interrupt Test, and The FIQ Interrupt Test. First, test each part separately, and then perform the overall system test.
(1) timer interruption Test
μC/OS-II requires a clock cycle (periodic scheduled interrupt) to achieve time delay and timeout. The clock cycle occurs 10 to 10 times per second ~ 100 times. In this design, the timer0 timer of box is used to generate the clock cycle of the system. The clock frequency is 50Hz. Create three tasks task_main, task_test and task_led to call the μC/OS-II system delay function ostimedly () in each task to realize the delay of different time length, through the serial port output signal, we can observe that the task can be delayed and scheduled according to the predefined settings.
(2) IRQ interruption Test
During the timer interrupt test, timer0 interrupt is set to IRQ interrupt. Then, add an IRQ interrupt. Set the External Interrupt eint4, 5/6, and 7 of the b0x to a key interrupt and add it to the system. When the key is pressed, the corresponding LED light is lit, at the same time, output the key information through the serial port. During the running of the program, the timer0 timer is interrupted at a fixed interval. during the running of the program, any buttons are randomly pressed, and the key interruption can receive timely response and accurate return.
(3) FIQ interruption Test
FIQ interruption is not managed by the operating system, and the interrupt response speed is fast. Therefore, the timer2 of b0x is used as the FIQ interrupt. In addition, the Interruption Frequency of the Tim-er2 is faster (set to 10 times the timer0 in the test), through the serial output of the interrupt information, FIQ interrupt can be normal response and return.
Set the above three types of interruptions in the system at the same time, and the system can run stably.

Conclusion 5
There are various types of microprocessors and operating systems in the embedded field. After combining different microprocessors and operating systems to form an embedded system, we need to design an interrupt system based on the characteristics of the two. For the design of the interrupt System of x and/OS-II, so that after the transplantation of μC/OS-II to the X system, the interruption can be effectively managed, and the execution efficiency of the system is improved, its design philosophy can also be applied to the design of other embedded interrupt systems. However, due to the Structure Problem of μC/OS-II, it is necessary to carry out specific analysis in practical application.