Interruption of STM32F1

1. What is the interruption and the role

The following excerpt from Baidu Encyclopedia

Middle finger when needed, the CPU temporarily stops the execution of the current program and executes the program and execution process to handle the new situation.

Interrupt processing: From the query-type transmission process can be seen, its advantages are small hardware overhead, use is relatively simple. But in this way, the CPU to constantly query the state of the peripheral, when the peripheral is not ready, the CPU can only cycle wait, can not execute other programs, so that the CPU wasted a lot of time, reduce the utilization of the host. In order to solve this contradiction, we put forward the interrupt transmission mode, that is, when the CPU main program operation, the peripheral data has been deposited into the data register of the input port, or the port data output register is empty, the peripheral through the interface circuit to the CPU to send the interrupt request signal, the CPU satisfies certain conditions, Suspend execution of the currently executing main program, into the execution of the corresponding input/output operation of the sub-program, when the input/output operation is completed, the CPU will return to continue to execute the original interrupted main program. In this way, the CPU avoids a lot of time spent on waiting, querying the status of the operation of the signal, so that its efficiency can be greatly improved. A device or event that can make an interrupt request to the CPU is called the interrupt source. The processing of the method is interrupted. That is, when the CPU (central processing unit) executes a current instruction, if the peripheral sends an interrupt request to the CPU, then the CPU will send an interrupt response signal when it satisfies the response, while shutting down interrupts, indicating that the CPU is not accepting interrupts from another device. At this point, the CPU will look for the device that interrupts the request source, and save the contents of the CPU's own program counter (PC). He then shifts to the interrupt service program that handles the interrupt source. The CPU will restore the site information after it saves the field information and equipment services (such as exchanging data). After these actions are completed, the opening is interrupted and returned to the next instruction of the original interrupted main program.

2. Basic knowledge of interrupts

The following is an excerpt from the STM32 Development manual

The CM3 core supports 256 interrupts, including 16 core interrupts and 240 external interrupts, with a programmable interrupt setting of 256 levels. But STM32 did not use all of the CM3 kernel, but only part of it. The STM32 has 84 interrupts, including 16 core interrupts and 68 unshielded interrupts, with a 16-level programmable interrupt priority. And we used to be these 68 can be shielded interrupt, but STM32 68 can be shielded interrupt, on the stm32f103 series above, only 60 (in 107 series only 68).

Register Group for Interrupt priority control: IPR[15]: The full name is: Interrupt priorities registers, this register group is very important. The interrupt grouping of STM32 is closely related to this register group. Because STM32 has more than 60 interrupts, the STM32 uses an interrupt grouping approach to prioritize interrupts. The IPR Register group consists of 15 registers of 32bit, each masking interrupt occupies 8bit, so that a total of 15*4=60 can be masked interrupts. The number of masked interrupts is equal to STM32. IPR[0] [31~24], [23~16], [15~8], [7~0] respectively, corresponding to the interrupt 3~0, and so on, a total of 60 external interrupts. The 8bit per shielded interrupt is not used in all, but only 4 bits high. These 4 bits are divided into preemption priority and sub-priority. Preemption priority is before, and child priority is behind. Each of these two priorities is determined by the set of interrupt groupings in SCB->AIRCR. Here is a brief introduction to the STM32 Interrupt grouping: STM32 breaks into 5 groups, group 0~4. The settings for this grouping are defined by the bit10~8 of the SCB->AIRCR register. The specific distribution relationship is shown in table 4.5.1:

With this table, we can clearly see the configuration relationship of the group 0~4, for example, the group is set to 3, then all 60 interrupts, the highest 3 bits in the high four bits of the interrupt priority register for each interrupt is preemption priority, and the low 1 bit is the response priority. For each interrupt, you can set preemption priority to 0~7, with a response priority of 1 or 0. The preemption priority level is higher than the response priority. The smaller the value, the higher the priority. There are two points to note here: First, if the preemption priority and the response priority of the two interrupts are the same, then the first execution is to see which interrupt occurs first, and second, the high priority preemption priority is the ability to interrupt the low preemption priority interrupt that is in progress. With the same priority interrupt, high priority response priority does not interrupt low-response priority interrupts.

In conjunction with an example, assume that the set interrupt priority group is 2, then set the preemption priority for interrupt 3 (RTC interrupt) to 2 and the response priority to 1. The preemption priority for interrupt 6 (external interrupt 0) is 3 and the response priority is 0. The preemption priority for interrupt 7 (external interrupt 1) is 2 and the response priority is 0. Then the order of priority for these 3 interrupts is: Interrupt 7> interrupt 3> interrupt 6.

To interrupt the priority setting:
1) Set interrupt grouping at the beginning of system operation. Determines the group number, which is the number of allocation bits that determine preemption priority and sub-priority. The calling function is Nvic_prioritygroupconfig ();
2) Set the interrupt priority level for the interrupt used. The function for each interrupt call is Nvic_init ();

some basic concepts of STM32 IO Port interrupts

Each IO of the STM32 can be used as an interrupt input for an external interrupt, which is also a powerful aspect of STM32. The normal IO port needs to be specified as a disconnect when used as an interrupt, i.e. the Exti interface. The stm32f103 interrupt Controller supports 19 external interrupt/event requests. Each interrupt has a status bit, and each interrupt/event has its own triggering and masking settings. The 19 external interrupts for the stm32f103 are:
Line 0~15: input interrupt corresponding to external IO port.
Line 16: Connect to the PVD output.
Line 17: Connect to the RTC alarm event.
Line 18: Connect to the USB wake-up event.
From the above can be seen, STM32 for the IO port use of only 16 interrupt line, but STM32 IO port is far more than 16, then STM32 is how to put 16 interrupt line and IO port one by one corresponds to it. So STM32 design, GPIO gpiox.0~gpiox.15 (X=a,b,c,d,e, f,g) respectively corresponding to the interrupt line 15~0. In this way, each of the broken lines corresponds to a maximum of 7 IO ports, taking line 0 as an example: it corresponds to gpioa.0, gpiob.0, gpioc.0, gpiod.0, gpioe.0, gpiof.0, gpiog.0. The interrupt line can only be connected to 1 IO ports at a time, so it needs to be configured to determine which GPIO the corresponding interrupt line is configured on.

3. How to use interrupts

1) Turn on the peripheral clock of the key and the relevant configuration of the key.

Rcc_apb2periphclockcmd (rcc_apb2periph_gpioa| rcc_apb2periph_gpioc| Rcc_apb2periph_gpiof| rcc_apb2periph_gpiog,enable);

Mode typically uses Gpio_mode_ipu, pull-up input

2) Initialize the relevant configuration of the LEDs.

3) Turn on the multiplexing clock (external interrupt, need to enable Afio clock)

Rcc_apb2periphclockcmd (rcc_apb2periph_afio,enable);

4) Specify medium break (take PG8 as example)-----4) 5) step is to set the interrupt line and GPIO mapping relationship, and then set the interrupt trigger mode and other initialization parameters

Gpio_extilineconfig (Gpio_portsourcegpiog,gpio_pinsource8);

5) Interrupt Initialization configuration

exti_initstructer.exti_line=exti_line8;//in the Wire 8
exti_initstructer.exti_mode=exti_mode_interrupt;//Interrupt Mode Trigger
xti_initstructer.exti_trigger=exti_trigger_rising_falling;//arbitrary mode triggering
exti_initstructer.exti_linecmd=enable;
Exti_init (&exti_initstructer);

6) Since it is interrupted, there is an interrupt channel (interrupt processing function), interrupt priority, STM32 IO Port external interrupt function only 6,

The following were:
EXPORT Exti0_irqhandler
EXPORT Exti1_irqhandler
EXPORT Exti2_irqhandler
EXPORT Exti3_irqhandler
EXPORT Exti4_irqhandler
EXPORT Exti9_5_irqhandler
EXPORT Exti15_10_irqhandler
Interrupt line 0-4 Each of the broken lines corresponds to a break function, a break in the 5-9 common interrupt function Exti9_5_irqhandler, the break 10-15 common interrupt function Exti15_10_irqhandler.

Nvic_initstructer.nvic_irqchannel=exti9_5_irqn;//pg8 in EXTI8, corresponding to EXTI9_5_IRQN
nvic_initstructer.nvic_irqchannelpreemptionpriority=2;
Nvic_initstructer.nvic_irqchannelsubpriority=1;
nvic_initstructer.nvic_irqchannelcmd=enable;
Nvic_init (&nvic_initstructer);

7) Edit Interrupt handler function, void Exti9_5_irqhandler (void)

In this function, first determine if an interrupt line has an interrupt, if (Exti_getitstatus (Exti_line8)!=reset)

If it happens, make the appropriate logical processing.

Finally, it is necessary to clear the interrupt flag bit on an interrupt line, Exti_clearitpendingbit (Exti_line8);