Introduction of IIC Bus

The I 2C Bus is a second-line bus for the connection between IC devices. It transmits data between devices connected to the bus via SDA (serial data line) and SCL (serial clock line) Two wires, and identifies each device according to the address: whether it is a microcontroller, a memory, an LCD driver, or a keyboard interface. I²c can be used to replace the standard parallel bus, can connect various integrated circuits and function modules. IIC-enabled devices include microcontrollers, ADCs, DACS, storage, LCD controllers, LED drivers, and real-time clocks. Using the I²c-bus standard microcontroller or IC device, its internal not only has an I²c interface circuit, but also the internal unit circuit according to the function divided into a number of relatively independent modules, through software addressing to achieve chip selection, reduce the device chip selection line connection. The CPU can not only connect a function unit to the bus by the instruction, but also can detect the working condition of the unit, so as to realize the simple and flexible expansion and control of the hardware system. The interface circuit structure of the I²C bus is shown in the following figure:

IIC Bus interface features

1. SCM serial interface of the transmission and reception generally each with a line, such as Txd and Rxd, and the I²c bus according to the function of the device through the software program so that it can work in the way of sending or receiving.

2. When a device sends a message to the bus, it is the transmitter (also known as the main device), and when it receives information from the bus, it becomes the receiver (also called slave device).

3. The main device is used to start transmitting data on the bus and generate the clock to open the transmitting device, at which point any addressed device is considered to be from the device. The control of the I²c bus is determined entirely by the address and data that are sent out by the main device attached to the bus.

4. The relationship between the master and slave (i.e., send and receive) on the bus is not immutable, but depends on the direction of the data transmission at this time.

The data transfer rate of the 5.I2C bus is 100kbit/s in the standard operating mode and the maximum transfer rate 400kbit/s in a fast manner.

6. The clock synchronization signal when transmitting information on the I²C bus is performed by the logic "and" of all devices hooked up to the SCL clock line. High-to-low jumps on the SCL line affect these devices, and once a device's clock signal jumps low, the SCL line remains low so that all devices on the SCL line start low.

7. When the clock signal of all devices jumps to high, the low-level period ends and the SCL line is released back to high, i.e. all devices start their high-level phase simultaneously. The first device that ends the high-level period then pulls the SCL line low. This creates a synchronous clock on the SCL line. It can be seen that the clock low time is determined by the device with the longest clock low period, while the clock high time is determined by the device with the shortest clock high-level period.

8. In the I²C bus specification, the definition of the start and end signals (also called start and stop signals) is shown in the following figure.

9. When the clock line SCL is high, the data line SDA is defined as the "start" signal from the high level jump to the low level;

10. When the SCL line is high, the SDA line has a low-to-high jump to an "end" signal.

11. Both the start and end signals are generated by the master device.

12. After the signal is started, the bus is considered to be busy, and the bus is considered idle for a period of time after the signal is closed.

IIC Bus data transfer format

1. After the I²C bus starts the signal, the first byte data sent is used to select from the device address.

(1) where the first 7 digits are address codes;

(2) The 8th position is the direction bit (r/w). The direction bit is "0" for sending, that is, the main device writes the information to the selected slave device, and the direction bit "1" indicates that the master device will read the information from the device.

2. There is no limit on the number of bytes of data transmitted on the I²C bus, but each byte must be 8 bits, and each transmitted byte must be followed by an approved bit (9th bit), also called the answer bit (ACK);

In order to complete a byte transfer, the receiver should send an ACK bit to the sender. An ACK should occur during the nineth pulse of the SCL line. When an ACK signal is received, the sender should release the SDA line so that the SDA line level is high. The receiver should drive the SDA line as low in the ACK pulse process. Therefore, during the high level of the nineth SCL Pulse