Introduction to 80x86 CPU registers

This blog post focuses on the features and functions of the CPU registers around the base part of the registers in the 80x86 CPU.

Objective

First, let's introduce the history of Intel CPUs.

Intel CPU Series, initially 4-bit microprocessor 4004, then to 8-bit microprocessor 8008, then 8-bit microprocessor 8080, and later 16-bit microprocessor 8086.
Starting from 8086, Intel entered the so-called x86 era.

Intel 8086 is a 16-bit CPU, and because the CPU before 8086 is 8-bit CPU, which also causes a lot of peripherals to support only 8-bit, so Intel immediately introduced a 8-bit 8088 CPU, so Intel 8088 can also As a 8086 8-bit version, if it is but from the assembly language point of view, 8086 and 8088 is no difference, that is, 8086 running programs can be migrated without modification to 8088, 8088 running programs can also be migrated without modification to 8086. Of course, there are some special places that are different, and these are basically overlooked here.

After the 8088 CPU, Intel introduced 80186, 80286, two CPUs are 16-bit CPUs. For 80186来, the difference between 8086 and 80,186 can be seen simply as a few more than a few instructions. And 80286 is different, 80286 of the address bus number has changed. On 8086, 8088, 80186, the address bus for the CPU is 20, and the maximum addressable 2^20 is the addressing capability of 1MB. And for the 80286 CPU, its address bus number reached 24, thus the maximum addressing capacity of 2^24 that is 16MB, due to support more physical memory addressing, so 80286 began to become a multi-tasking, multi-user system core.
Later, Intel introduced 80386, 80386 is a 32-bit microprocessor, the Intel 80x86 family of 32-bit microprocessors started at 80386, while 80386 is fully compatible with the previous 8086/8088,80186,80286, and 80386 full Polygons support 32-bit data types and 32-bit operations, and 80386 of the data bus root and address bus root numbers reach 32, allowing the maximum physical addressing to be 2^32 or 4GB.

The next 80486 is also a 32-bit microprocessor, and then came out of the Pentium and Pentium Pro, and so on the fifth generation microprocessor, these processors are 32-bit microprocessors, but their data bus and address bus has been expanded, such as the Pentium data bus to 64 Pentium Pro has an address bus number of 36 bits.

Well, the introduction of Intel CPU is here, and the following will begin to return to the center, looking at the registers in the CPU.

With all that said, what exactly is a register? In fact, a register is a unit that stores information, or a device, or a container. Like memory, memory is also a storage medium or a storage unit. For registers, it is functionally similar to memory, except that the registers are inside the CPU and the memory is outside the CPU. Registers are scarce resources in the CPU.

Register classification

The registers in the CPU are divided into the following registers:

• 4 Data registers (EAX, EBX, ECX, and edx)
• 2 Variable address registers (ESI and EDI)
• 2 pointer registers (ESP and EBP)
• 6 segment Registers (ES, CS, SS, DS, FS and GS)
• 1 instruction Pointer registers (EIP)
• 1 Flag Registers (eflags)

Data registers

Data registers are primarily used to store information such as operands and results of operations, thus saving the time required to consume the bus and access memory for the number of read operations. The 32-bit CPU has 4 general-purpose registers of 32-bit eax, EBX, ECX, and edx. Access to low 16-bit data does not affect data that is 16 bits high. These low 16-bit registers are named: AX, BX, CX, and DX, and they match the registers in the previous CPU.

4 16-bit registers can be divided into 8 separate 8-bit registers--AX:AH+AL,BX:BH+BL,CX:CH+CL,DX:DH+DL. Where, for *x16 bit registers, the *H represents a high-level 8-bit register, and the *L represents a low 8-bit register. At the same time, except for these 4 data registers, no other registers can be divided into two independent 8-bit registers. Each register has its own name and can be accessed independently. Programmers can use this "can-do" feature of data memory to flexibly handle word/byte information.

Notice the word "standalone" in the above sign, which indicates that AH and Al are used as 8-bit registers as if they were completely unrelated, that is to say, two completely unconnected registers X and Y. For example, the assembly instructions MOV AH, 12h,cpu at the root of the execution will not know what the Devil in Al, because it only know and manipulate AH.

For each data register, there is a difference in their functionality.

Register ax is often called an accumulator (accumulator), and operations with accumulators may take less time. Accumulators can be used to multiply and divide, input and output operations, and they are used very frequently.

Register BX is commonly referred to as the baseregister, which can be used as a memory pointer. Its exclusive functionality is addressing (addressing physical addresses). The data stored in BX register is usually used as an offset address, it is based on the base address of the segment address, combined with the offset address in the BX register, it can be addressed.

Register CX is often referred to as the count register (count register), which is used to control the number of cycles when looping and string operations are used, and the number of times a loop can be specified by CX when using loop loop instructions in assembly instructions In a bitwise operation, when shifting multiple bits, register CL is used to indicate the number of bits shifted.

Register DX is often referred to as the dataregister. It can participate in the operation as the default operand or the port address of the I/O when the multiply and divide operations are performed.

In a 16-bit CPU, AX, BX, CX, and DX cannot hold the address of a storage unit as a base address and a variable address register, but in a 32-bit CPU, its 32-bit registers eax, EBX, ECX, and edx can not only transmit data, hold data from scratch, but also act as a pointer register. Therefore, these 32-bit registers are more versatile.

Variable address register

32-bit CPUs have 2 general-purpose registers ESI and EDI. Its low 16 bits correspond to Si and di in the previous CPU, and access to low 16-bit data does not affect the high 16-bit data.

The SI (source index) is the source variable address register, and DI (Destination index) is the destination address register .

Registers esi, EDI, Si, and di are referred to as the variable address registers (Index register), which are mainly used to hold the offset of the memory cells in the segment, and they can be used to address multiple memory operands to facilitate access to the storage unit in different addresses. The variable address register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored. They can be used as a general memory pointer. During the execution of the string manipulation instructions, they have specific requirements, and they also have special functions.

Pointer Register

The 32-bit CPU has 2 32-bit general-purpose registers EBP and esp. Its low 16 bits correspond to the BP and SP in the previous CPU, and access to low 16-bit data does not affect the high 16-bit data.
Registers EBP, ESP, BP, and SP are called pointer Registers (Pointer register), mainly used for storing the offset of the storage unit in the stack, and they can be used to address multiple memory operands to provide convenient access to the storage unit in different addresses. The pointer register is not divisible into 8-bit registers. As a general register, you can also store operands and results of arithmetic logic operations.

They are primarily used to access storage units within the stack and provide for:

BP is a base pointer (base Pointer) register that allows direct access to data in the stack.

The SP is a stack-Pointer register that can only access the top of the stack.

Segment Register

Segment registers are set according to the management mode of memory fragmentation. The physical address of the memory unit is composed of the value of the segment register and an offset, which can be combined into a memory address that accesses a larger physical space with a value of two less digits.

The segment registers inside the CPU are:
ds--Code Segment Register, whose value is the segment value of the code snippet;
ds--Data Segment Register, whose value is the segment value of the data segment;
The ss--stack segment register (stack Segment register), whose value is the segment value of the stack segment;
es--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
fs--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The gs--additional segment register (Extra Segment register), whose value is the segment value of the additional data segment.

In a 16-bit CPU system, it has only 4 segment registers, so the program can be accessed directly at most 4 segments in use at any time, and in a 32-bit microcomputer system it has 6 segment registers, so programs developed in this environment can access up to 6 segments at the same time. There are two different ways to work with 32-bit CPUs: real-mode and protection-mode. In different ways, the function of the segment register is different. The relevant provisions are briefly described as follows:

Real mode: The first 4 segment registers CS, DS, ES, and SS have exactly the same meaning as the corresponding segment registers in the previous CPU, and the logical address of the memory unit is still the form of "segment value: Offset". To access data within a memory segment, the offset of the segment register and the storage unit must be used.

Protection mode: In this way, the situation is much more complex, the loading segment register is no longer a segment value, but a value called "Select Child (Selector)".

Instruction Pointer Register

The 32-bit CPU extends the instruction pointer to 32-bit and is credited as an EIP (instruction Pointer Register), with the lower 16 bits of the EIP acting the same as the IP in the previous CPU.

The instruction pointer eip and IP (instruction Pointer) are the offsets in the code snippet that hold the next instruction to be executed. In a system with prefetch instruction functionality, the next instruction to be executed is usually pre-provisioned to the instruction queue, unless a transfer situation occurs. Therefore, when you understand their functionality, there is no case of instruction queuing.

In real mode, since the maximum range for each segment is 64K, the high 16 bits in the EIP are definitely 0, which is equivalent to using only their low 16 bits of IP to reflect the order in which the instructions in the program are executed.

Flag Register (EFLAGS) operation result flag bit

• Carry Flag CF (Carry flag)
  The carry flag CF is mainly used to reflect whether the operation produces rounding or borrow. If the highest bit of the result of the operation produces a carry or borrow, its value is 1, otherwise its value is 0. The use of this flag bit is: the addition and subtraction of the number of characters (bytes), the size of the unsigned number comparison operation, the shift operation, the word (byte) between the shift, specifically change the CF value of the instructions.

• Parity Mark PF (Parity flag)
  The parity Mark PF is used to reflect the parity of the number of 1″ in the result of the operation. If the number of 1″ is even, the value of PF is 1, otherwise its value is 0.
  The PF can be used for parity checking, or for generating parity bits. In the process of data transmission, in order to provide the reliability of the transmission, if the use of parity method, you can use the flag bit.

• Auxiliary carry sign AF (auxiliary Carry flag)
  The value of the secondary carry Flag AF is set to 1 if the following occurs, otherwise its value is 0:
  in a word operation, when a low byte is taken to a high byte rounding or borrow;
  When a byte operation occurs, a low 4-bit high 4-bit carry or borrow is occurring.
  For the above 6 operation result flag bits, in the general programming case, the use frequency of the flag bit CF, ZF, SF and of is higher, while the use frequency of the flag bit PF and AF is low.

• 0 logo ZF (Zero flag)
  The 0 symbol ZF is used to reflect whether the result of the operation is 0. If the result of the operation is 0, its value is 1, otherwise its value is 0. This flag bit can be used when judging whether the result of the operation is 0 o'clock.

• Symbol SF (sign flag)
  The symbolic symbol SF is used to reflect the symbolic bit of the result of the operation, which is the same as the highest bit of the result. In the microcomputer system, the signed number uses the complement notation, so the SF also reflects the positive and negative sign of the result of the operation. When the result of the operation is positive, the SF value is 0, otherwise its value is 1.

• Overflow flag of (Overflow flag)
  The overflow flag of is used to reflect whether the signed number plus minus operation results in overflow. If the result of the operation exceeds the range that can be represented by the current number of operations, it is called overflow, and the value of of is set to 1, otherwise the value of of is cleared to 0. "Overflow" and "carry" are two different meanings of the concept, do not confuse. If you're not sure, check out the relevant chapters in the principles of computer composition course.

Status control Flag bit

The status control flag bits are used to control CPU operation, and they have to be changed by special instructions.

• Trace flag TF (TRAP flag)
  When the trace flag TF is set to 1 o'clock, the CPU goes into single step execution, that is, each execution of an instruction, resulting in a single step interrupt request. This method is mainly used for program debugging. There is no specific instruction in the instruction system to change the value of the flag bit TF, but the programmer can use other methods to change its value.

• Interrupt Allow flag if (interrupt-enable flag)
  The interrupt allow flag if is used to determine whether the CPU responds to an interrupt request made by a masked interrupt outside the CPU. However, regardless of the value of the flag, the CPU must respond to an interrupt request from an unshielded interrupt outside the CPU, as well as an interrupt request that is generated internally by the CPU. Specific provisions are as follows:
  when if=1, the CPU can respond to interrupt requests made by a masked interrupt outside the CPU;
  When if=0, the CPU does not respond to interrupt requests made by a masked interrupt outside the CPU.
  The instruction system of the CPU also has special instructions to change the value of the flag bit if.

• Direction Mark DF (Direction flag)
  The direction flag DF is used to determine the direction in which the pointer register adjusts when the string operation instruction executes. The specific provisions are given in section 5th 2.11--string manipulation instructions. In the instruction system of microcomputer, a special instruction is provided to change the value of the flag bit DF.

32-bit flag register increased flag bit

• I/O privilege flag iopl (I/O Privilege level)
  The I/O privilege flag is represented by a two-bit bits, also known as an I/O privilege level field. This field specifies the privilege level that requires the execution of I/O directives. If the current privilege level is less than or equal to the value of IOPL, then the I/O instruction executes, or a protection exception occurs.

• Nested Task Flags NT (Nested Task)
  Nested task Flags NT is used to control the execution of interrupt return instruction Iret. Specific provisions are as follows:
  when Nt=0, the EFlags, CS, and EIP are restored with the values stored in the stack, and the normal interrupt return operation is performed;
  When Nt=1, the interrupt is returned by the task transformation.

• Restart flag RF (Restart flag)
  Restart flag The RF is used to control whether the debug failure is accepted. Rule: When Rf=0, said "accept" debug failure, otherwise refused. After a successful execution of an instruction, the processor set the RF to 0, and when it accepts a non-debug fault, the processor will set it to 1.

• Virtual 8086-Way flag VM (virtual 8086 mode)
  If the value of this flag is 1, the processor is in the virtual 8086 mode of operation, otherwise, the processor is in a general protection mode of operation.

Introduction to 80x86 CPU registers