Introduction
ARM7 is a member of the 32-bit general-purpose microprocessor arm (advanced RISC machines) family, with relatively low powersource consumption and a good price/performance ratio,based on RISC structure, instruction set and related decoding mechanism and micro-programcontrol of the complex instruction system is relatively simple compared to the computer,This allows it to have higher command processing power and real-timeinterrupt response capability.
The instruction set consists of 11 basic types: ●Two types are used to offset the arithmetic logic unit, and in 31 registers (32 bits) betweenLine High-speed operation Barrel Shifter Multiplication device ●three types of instruction control data are transmitted between the memory and the register, one for elastic addresses one forhigh-speed content switching one for exchanging data
●three types of instructions for controlling process and privilege level execution ●three dedicated coprocessor for external control, this coprocessor allows the function of the instruction set to be open and unifiedformat extended to off-chip
Features:for high-level languages
The arm instruction set is suitable for compilers of different high-level languages, requiring critical code snippets, assembly language programmingalso very simple,Unlike other microprocessors,you need to rely on a complex compiler to manage instructions.
●Pipeline Technologyeach part of the instruction processing and storage system can be run continuously. A typical example,an instruction is being executed and the next instruction is being decoded,The third instruction is also removed from the memory. in a storage system, the design of the storage interface maximizes performance potential without the need for a significant cost .Speedallows system control functions to be applied to standard low-voltage logic, which pushesFast local access mode provided by industrial DRAM
compatibility
The ARM7 has a 32-bit address bus and all ARM processors share the same instruction set, ARM7 can be configured to 26-bitcompatible with other earlier processors.
CMOS
The ARM7 is a full-static CMOS, allowing the clock to be stopped in any part of the cycle, but without losing status.
Application:The ARM7 is suitable for applications that require compact and powerful RISC processor systems ●Telecom GSM Terminal Control ●Data Communication Protocol conversion ●portable computer Handheld computer ●Automatic control System engine management Unit ●Information Storage System memory card ●image processing Joeg controller
two. Programming ModeARM7 support for different operation configurations ●hardware configuration, controlled by input signal ●other for software control, calledoperating mode
Hardware configuration SignalThe ARM7 provides three hardware configuration signals that can be changed when the processor is running, as follows:
1. Big and Little endian (bigend bit) ARM7 the data in mem as a big Endian or Little Endian, depending on the bigned signal as high or lowtype,MEM is treated as byte-linear storage, with sequence numbers ranging from 0 up, bytes 0 to 3 for the first storage word, and 4 to 7 forthe second one, and so on
In the Littleendian format, the smallest byte of a word is treated as the lowest byte and the largest byte is treated as the highest byte. BYTE 0 will be linked to the data cable d[7:0]
In the big Endian format, the highest byte is present at the lowest address in mem, and the lowest byte is the highest address of Mem. Mem in byte 0 corresponds to the data line d[31:24],endianism only affects loading and storing instructions.
operation mode SelectionThe ARM7 has 32-bit addresses and 32-bit data cables. Processor supports byte (8-bit), Word (32-bit) data type, Word mustfour-byte alignment. instructions are executed by word, data operations (such as addition) are performed in words, and loading and storage operations can besend a word or byte.
ARM7 supports six modes of operation:(1) User mode (USR): Normal program execution State (2) Fiq mode (FIQ): Supports data transfer or channel processing (3) IRQ mode (IRQ): For General interrupt handling (4) Management mode (SVC) : Protected mode for operating system (5) exception mode (ABT): Data or instruction Prefetch exception entered (6) undefined mode (und): When no defined instruction is executed , it enters software control, external interrupt, exception Handling can change the mode of operation. Most of the applications are executed in user mode. (7) other modes, such as management mode, are entered when interrupts, abnormal services, or access to protected resources.
Register Device
ARM7 Processors Total 37 Registers ●31 X (32-bit) Universal registers ●6 Status Registersat any time16 General-purpose registers (R0-R15) and one or two status registers are visible to the processor. Visible Storagedepending on processor mode and other registers (banked registers) will be switched to support IRQ, FIQ, admin, exception,no processing of defined patterns. Exception mode, non-defined mode.
In all modes, 16 registers (R0-R15) can be accessed directly. In addition to R15, the other registers arewith registers,can be used to save data and addresses. R15 saves the value of the programmable counter PC when R15 is read, bit [1:0] for ' 0 ', bits [31:2] to save the value of the counter. The 17th Register (cpsr-current program status register) is also available as ato access the. It includes the conditional code and the current mode bit, which can be considered an extension of the PC. R14 can be used as a sub-program connection register, when executing a branch or connection instruction, you can save the value of R15. In thein other cases, it can be used as a general purpose register. r14_svc, R14_irq, R14_fiq, R14_abt, R14_und and R14Similarly, when an interrupt or an exception occurs, or an interrupt and an exception program, the branch and branch connection instructions are executed,you can save the return value of R15
The FIQ mode has 7 banked registers, which are mapped to r8-14 (R8_fiq-r14_fiq). Some FIQ programs do not need to store anywhat registers. User mode, IRQ mode, admin mode, no definition mode all have two banked registers, map toR13 and R14. These two banked registers allow each pattern to have its own stack pointer and L-link register. Management modelmode, IRQ mode, exception mode, and non-defined modes (more than two banked registers are required) toThe Register (r0-r12) of some or all of the calling programs in your own stack, so that you can use them indefinitelyRegisters (R0-R12), which are restored before the calling program returns. In addition, there are 5 Spsrs deposit(store programmable status register), copy CPSR when an exception occurs. Each privileged-level pattern has a SPSR
The format of the programmable status register is shown in Figure 6, N,z,c, and the V-bit condition code flag bit. These conditional code flags may be changed at the end of the arithmetic or logic operation of the processor, or it can be used as a condition in the program to determine whether the order is executed. I and F bits are interrupt-forbidden bits. When I set ' 1 ', the IRQ interrupt is forbidden and the Fiq interrupt is forbidden when F-set ' 1 '. M[4:0] is the pattern bit, which determines the operating mode of the processor. Table 2 explains the pattern bit m[4:0]. Not all combinations represent valid actions, only those that are clearly defined are valid. The low 28 bits (including i,f,m[4:0]) of the PSR Register are all used as control bits. If there are exceptions to produce these control bits will change , or in management mode, the control bits are changed by software. Unused bits are reserved bits, and their state can be preserved when the control bit and flag bits change. When checking the PSR State, the program does not need to rely on the value of the reserved bits to judge because they may be ' 1 ' or ' 0 ' in a future processor.
ExceptionWhen the normal program flow needs to be interrupted, the exception is generated, allowing the processor to perform interrupts generated by the peripheral (e.g.).before entering exception handling, the state of the processor must be saved so that the source program can continue execution after the exception has been processed. Can beThere are several anomalies that can occur at the same time.
When ARM7 handles an exception, the state is saved through the banked register. The contents of the PC and CPSR registers are copied to the correspondingIn R14 and SPSR, the mode bit m[0:4 in the PC and CPSR) is forced to change depending on the type of exception. In the exception-breaking process, if you want to prohibit other nesting that is difficult to manage exceptions, you can set the interrupt-stop flag bit. In the need to repeat into the interrupthandler, R14 and SPSR should be saved to the main mem stack before the interrupt is enabled;when SPSR registers to the stack or from the stack, it is important to note that the entire word (32 bits) must be transmitted, not justflag bit or control bit. When multiple exceptions are produced at the same time, the fixed precedence determines the order of the exception responses. Priority willexplained in later chapters
FIQFIQ (Fast interrupt Request) exception is generated externally and the Nfiq input is pulled down. This input can accept asynchronous conversions,before the processor's execution process is affected, a clock cycle is delayed to keep pace with the processor. This design supportsdata transfer or channel processing, there are enough private registers to transfer values that need to be saved in some applications (minimize switchingcosts). You can set the F flag bit in CPSR to mask the Fiq exception (in addition to the user mode), if f-bit is zeroed, ARM7at the end of each instruction, the output of the Fiq synchronizer is checked for low levels. when a FIQ low input is detected, ARM7 performs the following steps:(1) The next command to execute the address +4, save to R14_fiq, save the value of CPSR to Spsr_fiq (2) force m[4:0]=10001 (Fiq mode), set the CPSR f,i (3) force the PC to remove an instruction from address 0x1c
In order to return from Fiq, perform SUBS Pc,r14_fiq, #4 will restore the PC (from R14) and CPSR (from Spsr_fiq) andThe interrupted program that continues execution.
IRQAn IRQ (interrupt request) is a normal exception that generates an IRQ when the NIRQ input bit is low. It has a priority lower than Fiq, andand when the Fiq exception handler is entered, it is masked. At any time, the CPSR I position 1 can be blocked in this(except for user mode). When I is zeroed, ARM7 checks the output of the IRQ Synchronizer at the end of each instructionIf there is a low level. When an IRQ input is detected, ARM7 performs the following steps:(1) The next command to execute the address +4, save to R14_fiq, save the value of CPSR to Spsr_fiq (2) force m[4:0]=10010 (IRQ mode), set the CPSR of I (3) force the PC to remove an instruction from address 0x18
In order to return to normal from the IRQ state, perform subs Pc,r14_fiq, #4 will restore the PC (from R14) and CPSR (fromSpsr_fiq) and continue execution of the interrupted program.
Abnormal interruptsAn exception interrupt is generated by an external abort input. Abort indicates that the current memory access is not complete. For example, inin the virtual memory system, the corresponding data on the current address may have been moved from memory to disc, and before the access is complete,the processor action may be required to recover the data. ARM7 Check the abort signal during the memory access cycle, if there is a differentOften generated, ARM7 will perform one of the following two steps: (1) If the exception is generated (Prefetch exception) during instruction prefetching, the prefetch instruction is flagged as invalid, but the exceptionThe fault is not immediately generated. If the instruction is not executed, for example, a branch instruction in the assembly line,will not produce an exception, if the command is exported to the pipeline and will be executed, the exception is generated. (2) If the exception is generated during data access (data exception), the ARM7 action depends on the instruction type (A) A single data transfer instruction (LDR,STR) will write back the changed base address register, the exception handler must This is something to be noted. (B) Exchange instruction Exception (SWP), although external read-write access may occur, it is as if this directive did not be executed as (C) block data transfer instruction complete (ldm,stm), if write-back location 1, the base address will be changed. If normalcase, the instruction writes back to the base register (the base address in the LDM transport list),then write backbe banned. Whenwhen an exception is generated, all register write-back is forbidden. This means that when the LDM instruction is abnormal, the R15(always the last one is delivered) will remain.
When an instruction prefetch exception or data exception occurs, ARM7 does the following: (1) Save address (Exception instruction address plus 4 for instruction Prefetch exception, plus 8 for data exception) to R14_abt,save CPSR to Spsr_abt(2) Force m[4:0]=10111 (abnormal mode), I (3) in the position CPSR force the PC to remove an instruction from the address 0x0c (Prefetch exception) or 0x10 (data exception)
In order to return from an exception, execute subs Pc,r14_abt, #4 (Prefetch exception) or subs Pc,r14_abt, #8 (numberRestore the PC and CPSR and continue executing the instructions that were abnormal. When the appropriate MEM management software is in effect, the anomaly mechanism allows the 鐀 of the page-type virtual mem system required by the Roentgenium to execute. Processoran arbitrary address can be generated, and the MMU generates an exception if the data in the address is invalid. The processor enters the system software trap,The system software must identify the cause of the exception, make the requested data valid, and re-execute the instructions that were abnormal. Application does not requireknow the amount of effective mem it uses, and it doesn't need to be in an abnormal state.
Software interruptsThe software interrupt instruction (SWI) enters management mode from other modes. Typically, a special management function is requested. When the SWI instruction is executed, ARM7 performs the following actions: (1) Save the SWI instruction address plus 4 to r14_svc, save the CPSR value to Spsr_svc (2) Force m[4:0]=10011 (admin mode), set the CPSR in the I (3) Force PC to remove an instruction in address 0x80 in order to return from SWI, execute instruction movs pc,r14_svc, restore pc and CPSR values, return to SWI's nextinstructions.
undefined directive TrapsWhen ARM7 encounters an instruction that he cannot handle (chapter fourth: Instruction set), it provides this instruction to the site's co-locationManager. If the coprocessor can execute this instruction but is busy at the time, the ARM7 will enter a wait state until the associationThe Manager is ready or interrupt generation. If no coprocessor can handle this instruction, ARM7 will enter the undefined instruction trapThe trap.
When there is no coprocessor hardware in the system, traps can be used for coprocessor software simulation, or through software simulationextensions to the universal instruction set. When the ARM7 receives an undefined instruction trap, perform the following steps: (1) Save the undefined instruction or coprocessor instruction plus 4 to r14_und; save Cpsr to Spsr_und. (2) Force m[4:0]=11011 (no definition mode), set I (3) in CPSR Force the PC to remove an instruction in address 0x04 after the emulation failed instruction, in order to return from the trap, execute Movs pc,r14_und, restore CPSR and return to the Nonedefines the next instruction for the directive.
From for notes (Wiz)
Introduction to Arm (Advanced RISC machines)
