Introduction to cache and read operation principles of Cache/primary storage systems

 

The cache size is one of the important indicators of the CPU. Its structure and size have a great impact on the CPU speed. To put it simply, cache is used to store frequently-used or forthcoming data or commands. When these data or commands are needed, they are directly read from the cache, this is much faster than reading data from the memory or even the hard disk, which greatly improves the CPU processing speed.

The data exchange between the CPU and the cache is in the unit of "Word", while the data exchange between the cache and the primary storage is in the unit of "Block". A block consists of several words, it is fixed to reflect the concept of "saving the data that the sub-storage has just been accessed and its nearby small range of data.

When the CPU performs memory read operations, the master address can be divided into two types: Life and missed. For the former, you can directly read the required data from the cache. For the latter, you need to access the primary storage and transfer the entire block of the access unit from the memory to the cache, then modify the cache tag. If the cache is full, replace an old block with a certain replacement algorithm.

Data Cache (D-Cache) and Instruction Cache (Instruction Cache, I-Cache) are also divided in the first-level cache ). The two commands are used to store and execute the data respectively. They can be accessed by the CPU at the same time, reducing conflicts caused by contention for cache and improving the processor performance.

Separate commands and data are stored in the Command cache and data cache respectively. This separate cache technology facilitates the CPU to execute commands in the pipeline. In a pipeline, data operations of one command and another command are usually prefetch in the same operation cycle. If commands and data are used in a unified cache, this will cause a conflict between the command fetch and Data fetch access. The result of the conflict is that the pipeline is interrupted, this seriously affects the efficiency of the pipeline. The separate cache technology is used. Because the command fetch and Data fetch are performed in different caches at the same time, there is no conflict, which is conducive to the implementation of the pipeline.

The secondary cache is used to coordinate the speed between the primary cache and the memory. At first, the cache was only one level. Later, the processor speed was improved, and the level-1 cache was not enough. Therefore, the level-2 cache was added. The second-level cache is slower than the first-level cache and has a larger memory capacity. It is mainly used for temporary data exchange between the first-level cache and the memory. The "L1-level Cache-L2-level cache-primary memory" level is exactly the same as the above-mentioned cache working principle, that is, the CPU first accesses the L1-level cache, then access the L2 cache and primary storage.

Cache/Read operation principle of the primary storage system:

When the CPU tries to read a word from the primary storage, the memory address sent to the cache and the primary storage at the same time. At this time, the Cache control logic determines whether the word is in the cache based on the marked part of the address. If it is hit, the word is immediately submitted to the CPU. If it is not hit (not hit), the word is read from the master memory and sent to the CPU using the master memory read cycle, at the same time, the entire data block containing this word is read from the primary storage and sent to the cache. Because the memory access of the program is local, when a data block is obtained to meet an access requirement, the following multiple accesses may be reading other words in the block.

Figure 1 read operation principle of the cache/primary storage system

 

Figure 2 Cache read operation process diagram

 

 

Http://baike.baidu.com/view/27650.htm for more information

I also recommend two good articles on Cache http://www.eefocus.com/book/09-06/741961276059787.html

 

Http://www.tyut.edu.cn/kecheng1/2008/site04/courseware/chapter5/5-5-2.html