Introduction to Axi Bus

The Axi full name advanced Extensible Interface is an interface protocol that Xilinx introduced from the 6 series FPGA, primarily describing the way data is transferred between the master and slave devices. Continue to use in Zynq, version is AXI4, so we often see AXI4.0,ZYNQ internal devices have Axi interface. In fact, Axi is a part of the AMBA (Advanced microcontroller bus Architecture) proposed by arm, a high-performance, high-bandwidth, low-latency on-chip bus that is also used to replace the previous AHB and APB buses. The first version of Axi (AXI3) was included in the AMBA3.0 released in 2003, and the second version of Axi, Axi (AXI4), was included in the 2010 release of Amba 4.0.

AXI protocol has the following characteristics:
. The address/control of the bus is separated from the data channel;
. Support for misaligned data transfer;
. Only the first address is required in the burst data transmission;
. There is also a separate read/write data channel;
. Support for significant transfer access and disorderly access;
. Easier timing closure

AXI4 consists of three interfaces:
. Axi4--for high-performance memory-mapped requirements.
. Axi4-lite--for Simple, Low-throughput memory-mapped communication (for example, to and from control and status registers).
. Axi4-stream--for high-speed streaming data.

axi interconnect
The Axi protocol is strictly a point-to-point master-Slave interface protocol, and when multiple peripherals need to interact with each other, we need to add a Axi interconnect module, the Axi interconnect matrix, The function is to provide a switching mechanism that connects one or more Axi master devices to one or more axi slave devices (a bit similar to the switching matrix inside the switch). Xilinx provides us with an IP core axi_interconnect_1 to implement this interconnect matrix, which we can see in the previous example in XPS. This IP core can support up to 16 main devices, 16 slave devices, and if more interfaces are needed, you can add more than a few IP cores. For more information on Axi Interconnect, refer to the Xilinx official documentation DS768.

The AXI4 and Axi4-lite interfaces contain 5 different channels:
. Read Address Channel
. Write Address Channel
. Read Data Channel
. Write Data Channel
. Write Response Channel

Each of these channels is an independent Axi handshake protocol. The following two graphs show the model of Read and write, respectively:

There are 9 Axi interfaces in Zynq, mainly for the interconnection of PS and PL, including the following three types:
. AXI_ACP interface, an interface defined by the arm multicore architecture, is translated as an accelerator conformance port for managing non-cached Axi peripherals such as DMA, and the PS end is the slave interface.
. The AXI_HP interface is a high performance/bandwidth AXI3.0 standard interface with a total of four, PL modules connected as primary devices. Mainly used for PL access to the memory on PS (DDR and on-chip RAM)
. The AXI_GP interface, which is a generic Axi interface, has a total of four, including two 32-bit primary device interfaces and two 32-bit slave-device interfaces.

In fact, in the specific design we often do not need to connect this place to do too much work, as in the previous example, we joined the IP core, the system will automatically use the Axi interface to connect our IP core with the processor, we just need to do a little more to add. However, this part of the concept is better understood.

Introduction to Axi Bus