Introduction to IC System composition

What is an IC system?

For algorithmic engineers, IC systems are hardware that accomplishes specific functions.
For architects, IC systems include controls, operations, and storage parts.
Circuit Design Engineer, IC system is adder, multiplier, and non-gate, op amp, switch capacitor and so on collocation.
For the layout engineer, it is a combination of polygon composition.

A common IC system consists of:

• Digital section (may include microprocessor, control circuit, data path, etc.)
• Simulation section (may include PLL,A/D,RF, etc.)
• Connection
• I/O PAD
• Memory

Number part
The majority of digital systems adopt the synchronous design method, that is, the clock is used to coordinate the operation of each part of the system. It consists of a combination of logic and sequential units (registers and latches), the data in the time series unit-combinatorial logic-sequential unit of the structure of the first level of transmission down. It is generally possible to roughly divide the digital part into the data path part and the control section. Data path part refers to the multiplier, adder, finite response impact filter (FIR) and other rules of the operating unit, the control part refers to the control of the flow of data management logic.

Simulation section
? ADC for analog-to-digital conversion
? DAC for digital-to-analog conversion
? Programmable gain amplifier PGA
? Phase-locked Loop PLL

I/O section
I/O is an interface between an IC system and an external environment. Foundry provides a comprehensive library, usually including three types of pad units: input pad, output pad, two-way pad. In the design, these pads can be considered as standard units, the direct example of the can be.

Memory
Memory is critical for the entire chip design:
? In high-speed IC design, memory bandwidth has become a performance bottleneck.
? Memory accounts for over 70% of the total chip area
? Memory consumes most of the power consumed by the chip
We generally do not need to design their own memory in the actual design, just according to the need (depth, speed, area, power consumption, etc.) using memory compiler directly generated, the other people provide the memory unit can be spliced together. When using memory, you need to be aware of whether the interface timing meets the requirements. (for example, in the design of 2D/GPU, I use the memory compier to generate various SRAM as required)

Connection
The connection includes the chip's signal connection, the power cord and the clock line.
? In deep submicron designs, wires cannot be simply viewed as ideal connections, and metal wires have capacitive, resistive, and inductive effects. These parasitic effects affect the integrity of the signal, and signal integrity and timing convergence are closely related. Often, crosstalk makes timing worse and more difficult to converge.
The capacitive parasitic effect of the wires causes the coupling of the signal line, which causes crosstalk (cross talk), which can affect timing, cause setup/hold violation, and may affect function, which causes the chip to not work properly.
The resistive parasitic effect of the connection causes a significant voltage drop, which affects the signal level. In an IC system, which is powered by a power supply network, a digital system must be able to function normally, and it has to provide a stable DC voltage for its logic unit, and the fluctuation of this voltage should be as small as possible. As the size of the chip increases, the current inside the chip becomes larger and more difficult to meet the voltage stability. Widening the wire reduces the resistance, thereby reducing the pressure drop and increasing the allowable peak current, but also consumes too much area.
If the connection is too long or the circuit speed is very high, the inductance effect of the wire will become significant. The inductance effect is difficult to deal with, but fortunately most of the current designs have very small inductance effects and are negligible.
? Wiring also causes the design timing to be difficult to converge.
Logic synthesis can not know the specific connection information, often using the Wireload model to estimate the connection delay. This model is not accurate, so it can be difficult to converge after p&r, thus evolving the physical synthesis technology.

As for what is physical synthesis, and the difference between it and logic synthesis, I'll explain it in a later post.

Resources

The basics of IC design

Introduction to IC System composition