Introduction to logical design

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The fourth part is hard to understand and has doubts (marked red). After the second clock cycle, reg1 should be 1. Introduction to logical design

First of all, in the logic Design Medium OpenGL /V HDL Is the least important knowledge. If you want to use Learning To grasp the logic design, it would be a big mistake. Basic knowledge for logical design: 1) CMOS circuitPrinciple It is the foundation of logical design, just as mathematics is the foundation of all natural sciences. The basis of the CMOS circuit determines your understanding of some problems in the logic design (such as the pressure steady state. 2) Number ASIC For the design method, you can find a book that introduces the design of digital IC to read it (note that it is not an introduction to OpenGL/VHDL ). System Design and SOC design methods and implementation. After reading these two books, you should master the following knowledge: synchronous design, cross-site Clock Domain Signal The basic process of ASIC design. (3) The last step is the OpenGL/VHDL. Language In my opinion Comprehensive A book is enough. 2) how to pay attention to the learned knowledge in practice is the focus of this article. A digital circuit is basically divided into a control type and an operation type. The so-called operation type is the input data (usually from memory) after some operations and then the output (usually to memory). A typical operation type circuit is Filter It is characterized by complex and intensive operations and relatively simple control. In fact, this is also the advantage of hardware, and most of the projects Module All belong to this category. The design of an operational circuit can be divided into two parts: data path design and control logic design. Generally, a data path is designed first. The so-called data path is the path from input to output, which generally includes logical operations, multiplexing, registers and even memory. Data paths generally determine the performance (speed, area, etc.) of the circuit. All logic design techniques are designed to optimize the data path. After the data path is complete, the designer starts to draw Time Series Graph. If the data path determines the quality of the design scheme, the control logic determines the right and wrong of the design. The so-called control signal is the control signal on the interface, the enable signal of the registers in the data path, the signal selected by the multi-channel and memroy control signal. The time sequence diagram of the control signal is based on the time sequence diagram of the data stream. It is easy to pass through the timing diagram of the control signal. State Machine Even counters are used to generate control signals. It should be noted that not all control signals must be generated directly by the state machine or counter, or by the unit delay or logic operation of other control signals. In short, the design of the control logic is relatively random, and the impact on the area is relatively small. As the name suggests, a control circuit has complicated controls, and many data path branches, but its operation logic is relatively simple. Common modules include UART, I2C, and even CPU. There is an extreme situation where only the control logic is available without data access, such as beverage machine, traffic light, clock, and Elevator Controller. I personally think that the hardware design of these modules has neither practical nor teaching significance. Although Beginners I think it is very challenging, but the design of the state machine has no technical depth. In addition, these modules are often misleading and out-of-the-box for beginners. Software Design Ideas to design hardware, such as drawing a flowchart. Of course, it is necessary for some control module flowcharts, but the most important thing for beginners is RTL And Program Therefore, computational circuits are more suitable for beginners to learn. However, the computational circuit has a major obstacle for scholars, that is, the calculation process is often complicated. We need to use C model to describe and generate test vectors and comparison results in advance. C Language There are certain requirements. Not through observation Waveform It is a professional practice to verify the correctness of the design through automatic comparison. Another problem is that computing circuits involve background knowledge. For example, a filter requires the designer to have a certain foundation for digital signal processing, it is estimated that this is also the reason why a large number of reference books are introduced to the design of the logic-based design. Here I recommend "Digital Signal Processing FPGA Implementation: although most of the content is obscure (at least for me), even if I only watch 1/10, it will be of great help to improve my own level. 3) When beginners equate RTL with a program, they do not have a perceptual knowledge of the integrated RTL results, or feel unable to start with a project, they all come from a problem: complicate the timing control process. What kind of counters, shift registers, state machines, etc. The representation is that RTL is very difficult and powerful! In essence, RTL is much simpler than C. The so-called RTL is the description of the register transmission level. The basic component is the logic gate and register. Everyone should have a good idea about combined logic modeling, but the output is an input expression. Use assign description, wire Declaration for output signals, always description, Reg Declaration for output signals, and all input signals are in the sensitive signal list. Timing modeling is actually quite simple: edge-triggered registers! YesAsynchronous Reset: Always @ (posedge CLK or negedge rst_n) If (~ Rst_n) Dout <= 0; Else Dout <= din; Or if there is no reset signal: Always @ (posedge CLK) dout <= din. In the synchronous circuit, clock is enough for both! It should be pointed out that although some libraries provide Synchronous Reset and enable registers, it is actually still obtained by the second register plus some combination logic: Always @ (posedge CLK) If (RST) Dout <= 0; Else if (en) Dout <= din; Equivalent: Assing din1 = rst? 0: En? Din: dout; Always @ (posedge CLK) dout <= din1; that is, a three-choice MUX and a non-Reset register. For example, a counter is generally described as follows: Always @ (posedge CLK or negedge rst_n) If (~ Rst_n) Count <= 0; Else if (count_en) Count <= count + 1; Essentially: Assign CNT = count + 1; Assign din = count_en? CNT: count; Always @ (posedge CLK or negedge rst_n) If (~ Rst_n) Count <= 0; Else Count <= din; That is, the logic of adding 1, one MUX and one set of registers. Shift registers can also be implemented in this way. I suggest beginners use the latter method to describe your design as much as possible, although Code But the actual circuit is the same as the former, and the latter's description is more closely related to the circuit. 4) Let's Talk About the synchronization design. As far as I know, many beginners do not have the concept of synchronization. The performance is that the clock is messy and even proud to be able to use latch. The most typical synchronization design is that there is only one clock, and all triggers store data along the same clock. For example: Always @ (posedge CLK) reg0 <= din; Always @ (posedge CLK) reg1 <= reg0; Assume that the initial values of reg0 and reg1 are 0 and 1 respectively. Din is 1 before the first rising edge of CLK, and the value of DIN is 0 before the arrival of the second Rising edge and remains unchanged. Then, after the first rising edge, reg0 loads din value 1, while reg1 loads reg0's initial value 0, Reg1 is changed to 0 only after the second Rising edge arrives. . Most people have no objection to the above description, but some people will immediately have another question: Why is the initial value of reg0 when reg1 loads when the first rising edge arrives, instead of the current value. To ensure that reg1 obtains the initial value of reg0, The reg1: Always @ (negedge CLK) reg1 <= reg0. They have this concern because they do not know that the final gate-level description does not have only two registers. In fact, there are several inverter latencies between the input from reg0 output to reg1 and the clock ends of reg0 and reg1. EDA Tool. Therefore, there is a default premise between the designer and the EDA tool, that is: the time when the value of reg0 reaches the reg1 input end is between the time when the current clock arrives at reg1 and the time before the next clock arrives at reg1. It can be understood that the timing relationship is default in the synchronous design, and the designer does not need to care, which greatly simplifies the design.