Introduction to Pipelining (Pipe-line)

1, what is the pipeline design technology?

A: The so-called pipeline design is actually a larger, more hierarchical combination of logic circuit divided into several stages, at each level inserted register group and staged data.

The K-Class is a K-register group with no feedback circuitry from top to bottom.

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2, the pipeline design in-depth explanation:

10.7 Combined Logic Design--Pipeline design

Pure combinatorial logic takes time: [Max (T1,T3) +t2]

Pipeline design First takes time: [Max (T1,T3) +t2]+2tco

Time required for pipeline design to stabilize : [Max (Max (T1,T3) +tco, (T2+tco))]

Pipeline design requires two clock cycles for the first time to get data, but then only one clock cycle is needed to get the data.

Pipelining is designed to improve throughput (throughput).

The performance improvement of pipeline design is at the expense of the resources of more register groups.

Pipeline design for simple combinatorial logic, the pipeline design occupies less resources, the general FPGA fully meet the requirements.

　　Pipeline design is necessary for complex combinatorial logic designs, because in order to ensure that intermediate calculations are obtained in the same clock cycle, more registers must be added between the levels.

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3. pipelined adder and Combinatorial logic adder

As can be seen from the schematic, basically every line has a register, but our final output is in the time when the CLK signal arrives at the output. The continuity of the operation is ensured.

Although the logic gate has increased, throughput and speed have increased.

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4. pipelined multiplier and combinational logic multiplier

Although I can't understand what the book says, we can see from the results that the pipelined multiplier is much faster than the combined logic multiplier, but it also takes up a lot of resources.

The so-called consumption of resources in exchange for speed ...

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Introduction to Pipelining (Pipe-line)