I/O characteristics

IO Resources

IO is a channel for communication and control with the outside world, and FPGAs provide a rich IO and some practical features.

This paper briefly extracts the main features to make reference for the design. Specific parameters refer to Handbook.

Part I: Overview of IO Features

-----through the flexible configuration of the software, can adapt to different electrical standards and I/O physical characteristics, can adjust the matching impedance characteristics, up and down pull resistance, you can adjust the output drive current size and so on.

Programmable pull-up (each Cyclone II device I/o pin provides an optional programmable

Pull-up resistor during user mode. If you enable the feature for an I/O

PIN, the pull-up resistor (typically KΩ) holds the output to the VCCIO

Level of the output pin ' s bank.)

The output buffer for each Cyclone II device I/O pin has a programmable

Drive strength control for certain I/O standards. The LVTTL, LVCMOS,

SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18 Class I and II, and

HSTL-1.5 class I and II standards has several levels of drive strength that

You can control. Using minimum settings provides signal slew rate

Control to reduce system noise and signalovershoot. Table 2–16shows

The possible settings for the I/O standards with drive strength control.

-----Bus-Hold and tri-State output (bus hold and pull-up conflict)

Each Cyclone II device user I/O pin provides an optional bus-hold

Feature. The Bus-hold circuitry can holdthe signal on an I/O pin at its

Last-driven state. Since The Bus-hold feature holds the Last-driven state of

The pin until the next input signal ispresent, an external pull-up or

Pull-down resistor is isn't necessary to hold a signal level when the bus is

Tri-stated.

The IO of the--------FPGA is not the same as the MCU, its IO and the power of the core are separate.

We can configure the IO voltage according to the device characteristics such as 3.3v 2.5v 1.8v, etc.

At the same time more advanced interface can be used such as PCI LVDS RSDS SSTL SDRAM and so on.

The Cyclone II architecture supports the Multivolt I/O interface feature,

which allows Cyclone II devices in all packages to interface with systems

of different supply voltages. Cyclone II devices have one set of Vccpins

(Vccint) that power the internal device logic array and input buffers that

Use the LVPECL, LVDS, Hstl, or SSTL I/O standards. Cyclone II Devices

Also has four or eight sets of VCC pins (VCCIO) that power the I/O

Output drivers and input buffers that use the LVTTL, LVCMOS, or PCI

I/O standards.

The Cyclone II Vccintpins must always being connected to a 1.2-v power

Supply. If the Vccintlevel is 1.2 V and then input pins be 1.5-v, 1.8-v, 2.5-v,

and 3.3-v tolerant. The vcciopins can connected to either a 1.5-v,

1.8-v, 2.5-v, or 3.3-v power supply, depending on the output

Requirements. The output levels is compatible with systems of the same

Voltage as the power supply (i.e., when Vcciopins is connected to a

1.5-v power supply, the output levels is compatible with 1.5-V systems).

When Vcciopins is connected to a 3.3-v power supply, the output high

is 3.3-V and is compatible with 3.3-V systems. Table 2–20summarizes

(Each Cyclone II device I/o pin is fed Byan IOE located at the ends of LAB

Rows and columns around the periphery of the device. I/O pins support

Various single-ended and differential I/O standards, such as the 66-and

33-mhz, 64-and 32-bit PCI Standard, Pci-x, and the LVDS I/o Standard

At a maximum data rate of 805 Megabitsper second (Mbps) for inputs and

640 Mbps for outputs. Each IOE contains a bidirectional I/O buffer and

Three registers for registering input,output, and output-enable signals.

Dual-Purpose DQS, DQ, and DM pins along with delay chains (used tophase-align double data rate (DDR) signals) provide in  Terface support for external memory devices such as DDR, DDR2, and single data rate (SDR) SDRAM, and qdrii SRAM devices at  Up to 167 MHz. ）

------Some FPGA pins are compatible and easy to upgrade extensions.

-------unused clock pin can be input

(The I/O pin counts for the EP2C5, EP2C8, and ep2c15a devices include 8 dedicated clock pins the can is used for data INP UTs. ）

-----------IO delay programmable

The Cyclone II device IOE includes programmable delays to ensure zero

Hold times, minimize setup times, or increase clock to output times. The Quartus II Compiler can program these delays to automatically minimize setup timewhile providing a zero hold time.

------Programmable IO power-up level

The IOE registers in each I/O block share the same source for clear or

Preset. You can program preset or clear for each individual IOE, but both

Features cannot be used simultaneously. can also program the

Registers to power on or low after configuration are complete. If

Programmed to power up low, an asynchronous clear can control the

Registers. If programmed to power Uphigh, an asynchronous preset can

Control the registers. This feature prevents the inadvertent activation of

Another device ' s active-low input uponpower up. If One register in an

IoE uses a preset or clear signal then all registers in the IoE must use that

Same signal if they require preset or clear. Additionally a synchronous

Reset signal is available for the IOE registers.

----Rich external Memory Control interface

Cyclone II devices support a broad range of external memory interfaces

such as SDR SDRAM, DDR SDRAM,DDR2 SDRAM, and Qdrii SRAM

External memories. Cyclone II devices feature dedicated high-speed

Interfaces that transfer data between external memory devices

167 mhz/333 Mbps for DDR and DDR2 SDRAM devices and

167 mhz/667 Mbps for qdrii SRAM devices. The programmable DQS

Delay chain allows fine tune the phase shift for the input clocks or

Strobes to properly align clock edges as needed to capture data.

In Cyclone II devices, all the I/O banks support SDR and DDR SDRAM

Memory up to 167 mhz/333 Mbps. All I/O banks support DQS signals

With the DQ bus modes ofx8/x9, orx16/x18. Table 2–14shows the

External memory interfaces supported in Cyclone II devices.

Part II: Pins and IoE

First look at the Cyclone II series pin count

IO Overall Features

Ioes support many features, including:

Differential and single-ended I/O standards

3.3-v, 64-and 32-bit, 66-and 33-mhz PCI Compliance

Joint Test Action Group (JTAG) boundary-scan test (BST) support

Output Drive Strength Control

Weak pull-up resistors during configuration

Tri-state buffers

Bus-hold Circuitry

Programmable pull-up resistors in user mode

Programmable input and output delays

Open-drain outputs

DQ and DQS I/O pins

Vrefpins

IOE structure

Configuration pins: (see Altera Cyclone series configuration documentation for specific usage)

MSEL[1:0] is used to select configuration modes such as AS, PS, etc.

The DATA0 FPGA serial data input is connected to the serial data output pin of the configuration device.

The DCLK FPGA serial clock output provides a serial clock for the configuration device.

NCSO (I/O) fpg** selected signal output, connected to the NCS pin of the configuration device.

The ASDO (I/O) FPGA serial data output is connected to the ASDI pin of the configuration device.

Nceo can be output during the download chain. In a download chain, when the first device is configured, the signal will start to be configured for the next device. The Nceo of the last device on the download chain is dangling.

The NCE download chain device can be input, connected to the Nceo of the previous device, and the last device of the download chain is nce grounded.

Ncnfig User mode to configure the start signal.

Nstatus Configure the status signal.

Conf_done Configure the end signal.

Power PIN:

Vccint core voltage. 130nm for 1.5v,90nm to 1.2V

VCCIO Port voltage. Generally 3.3V, can also support a variety of voltages, 5V, 1.8V, 1.5V

VREF reference Voltage

GND Signal Ground

Clock pins:

VCC_PLL PLL pin voltage, direct connection to Vccio

VCCA_PLL PLL analog voltage, cut-off via filter to Vccint

GNDA_PLL PLL Analog Ground

GNDD_PLL PLL Digital Ground

CLK[N] PLL Clock input

Pll[n]_out PLL Clock Output

Special pins:

VCCPD for the search drive

Vccsel for controlling the input buffer voltage associated with the configuration pin and PLL

Prosel power-on Reset option

Niopullup the internal pull-up resistor used to control the user I/O used in the configuration is working

Tempdioden for correlated temperature sensitive diodes

Other Special pins:

Original address: Special pin description of FPGA Tengfeixinxiang

1/1.I/O, ASDO

In the as mode is a dedicated output pin, in PS and JTAG mode can be used when the I/O foot. In the as mode, the foot is the CII that sends a control signal to the serial configuration chip. It is also used to read configuration data from the configuration chip of the foot. In the as mode, the ASDO has an internal pull-up resistor that has been in effect until the configuration is complete and the foot becomes a tri-state input pin. The ASDO foot is directly connected to the ASDI foot (5th foot) of the configuration chip.

2/2.i/o,ncso

In the as mode is the dedicated output pin, which can be used when the I/O pin is in PS and Jtag mode. In the as mode, this foot is the enable pin that CII uses to send to the external serial configuration chip. In the as mode, the ASDO has an internal pull-up resistor that has been in effect. This foot is active at low level. Directly to the/cs foot (1th foot) of the configuration chip.

3/3.i/o,crc_error

When the error detection CRC circuit is selected, the foot is used as the crc_error foot, if not the default to do I/O. However, it is important to note that this foot does not support open-drain and reverse. When it is crc_error, the high output indicates a CRC checksum error (an error occurred while configuring the SRAM bits). The support of the CRC circuit can be added in the setting. This foot is generally used in conjunction with nconfig feet. That is, if the configuration process fails, reconfigure.

4/4.i/o,clkusr

When the Enable user-supplled start-up clock (CLKUSR) option is turned on in the software, the foot is only available as a user-supplied initialization clock input pin. After all configuration data has been received, the conf_done foot becomes high, the CII device also requires 299 clock cycles to initialize registers, I/O and so on, the FPGA has two ways, one is to use the internal crystal oscillator (10MHZ), the other is from the CLKUSR The incoming clock (max. 100MHz). This feature slows down the time that the FPGA will start to work and can be used in special applications that require synchronization with other devices.

7/13.i/o,vref

Used to provide a reference level for certain differential standards. If it is not used, it can be used as I/O.

14/20. DATA0

Dedicated input feet. In the as mode, the configuration process is: CII will NCSO low level, configuration chip is enabled. CII then works with DCLK and ASDO, sending commands to the operation, and reading the address to the configuration chip. The configuration chip then sends data to CII via the data pin. The DATA foot is attached to the DATA0 foot of the CII. After the CII receives all the configuration data, it releases the conf_done foot (i.e. not forcing the conf_done foot low) and the Conf_done foot is open-drain (open-drain). At this point, because the conf_done is externally connected with a 10K resistor, it becomes high. At the same time, CII stops DCLK signals. After the conf_done becomes high (and then it becomes an input pin), the initialization process begins. Therefore, conf_done this foot outside must take a 10K resistor, to ensure that the initialization process can start correctly. The DATA0,DCLK,NCSO,ASDO has a weak pull-up resistor on the foot and is always active. After the configuration is complete, these pins become input tri-states and are set to high level by the internal weak pull-up resistor. In the as mode, the DATA0 receives the data (2nd foot) of the configuration chip.

15/21. DCLK

PS mode is input, as mode is output. In PS mode, the DCLK is a clock input pin that is the clock that the external device transmits the configuration data to the FPGA. The data is on the rising edge of the DCLK data, in the as mode, the DCLK foot is a clock output pin that is provided with a configuration clock. Directly to the configuration chip dclk foot up (6th foot). Regardless of the configuration mode, the foot becomes tri-state when the configuration is complete. If the external configuration device is configured, the device is configured to place the DCLK pin low. If you are using a master chip, you can set the DCLK high or the DCLK low. When the configuration is complete, triggering the foot does not affect the configured FPGA. This pin has input buffer, which supports the hysteresis function of Schmitt trigger.

16/22. NCE

Dedicated input feet. This foot is a low-active chip-selectable enable signal. The NCE foot is configured to enable the foot. In configuration, initialization, and user mode, the NCE foot must be low. During the configuration of multiple devices, the first device's nce foot is lowered, and its nceo is connected to the next device's nce foot, forming a chain. The nce foot is also required to lower the nce foot in JTAG programming mode. This pin has input buffer, which supports the hysteresis function of Schmitt trigger.

20/26. Nconfig

Dedicated input pins. This pin is a configuration control input foot. If the foot is lowered in user mode, the FPGA loses its configuration data, enters a reset state, and resets all the I/O pins to tri-state. The process of nconfig from low-level to high-level will initialize the reconfiguration process. If the configuration scheme uses an enhanced configuration device or EPC2, the user can connect the nconfig pin directly to VCC or to the ninit_conf foot of the configuration chip. This pin has input buffer, which supports the hysteresis function of Schmitt trigger. In fact, in user mode, the nconfig signal is used to initialize the reconfiguration. When the nconfig foot is lowered, the initialization process begins. When the nconfig foot is lowered, the CII is reset and enters the reset state, the Nstatus and conf_done feet are lowered, and all the I/O feet enter the tri-state. The nconfig signal must remain at least 2us. When the nconfig is back on the high level, the Nstatus is released again. The reconfiguration begins. In the actual application process, the Nconfig pin can be connected to a 10K pull-up resistor to 3.3V.

40/56. Dev_oe

I/O foot or global I/O enable foot. In the Quartus II software you can enable the Dev_oe option (enable device-wideoutput enable), if this function is enabled, the foot can be the global I/O enable foot, the function of this foot is, if it is low, all I/O are in the tri-state.

75/107. Init_done

I/O foot or open-drain output pin. When the foot is enabled, the jump from low to high on the foot indicates that the FPGA has entered the user mode. If the Init_done output PIN is enabled, after the configuration is complete, the foot cannot be used as user I/O. Inside the quartusii can be enabled by enabling the Enable Init_done Output option to enable this foot.

76/108. Nceo

I/o foot or output pin. When the configuration is complete, the foot outputs a low level. During the configuration of multiple devices, the foot is connected to the nce foot of the next device, which also requires a 10K pull-up resistor outside to Vccio. During the configuration of multiple devices, the Nceo of the last device can float. If you want to use this foot as a usable I/O, you need to set it up in the software. In addition, even if you do I/O, you have to wait until the configuration is complete.

82/121. Nstatus

This is a dedicated configuration state foot. Two-way foot, when it is output foot, is open drain. After power-up, the FPGA immediately resets the nstatus foot to a low level, and after the reset (POR) is complete, release it and set it to high. As the status output pin, if any error occurs during the configuration process, the nstatus foot will be lowered. As the status input pin, during configuration or initialization, the external control chip can pull the foot low, the FPGA will enter the wrong state. This foot cannot be used as a normal I/O pin. The nstatus foot must pull up a 10K ohm resistor.

83/123. Conf_done

This is a dedicated configuration state foot. Two-way foot, when it is output foot, is open drain. When the pin is output as a status, it is set to low level before and during the configuration. Once the configuration data is received and there are no errors, the initialization cycle starts and the Conf_done is released. When entering a pin as a state, when all data is received, it is set to high. The device then starts to initialize and then enters user mode. It cannot be used as normal I/O. This foot must also be connected to a 10K ohm resistor.

84/125,85/126. MSEL[1:0]

These feet are connected to a 0 or power supply, indicating high or low levels. 00 means using as mode, 10 for PS mode, and 01 for fast as mode. If Jtag mode is used, the JTAG mode has nothing to do with Msel, that is, with Jtag mode, Msel is ignored, but because they cannot float, it is recommended to receive it.

142/206 DEV_CLRN

I/O or global clear 0 input. In Quartus II, if you select the Enable Device-wide Reset (DEV_CLRN) function. This foot is the global clear 0 end. When the foot is lowered, all registers will be zeroed out. This foot does not affect the JTAG boundary scan or the programmed operation.

Advanced interfaces and speeds supported:

More detailed parameter Reference device Handbook

I/O characteristics