Is your op-amp going to vibrate?

Analog designers spend a lot of time designing amplifiers to stabilize the amplifier, but in practice there are many things that can cause these amplifiers to oscillate. There are many kinds of loads that can cause them to whine. Feedback networks that are not properly designed can cause them to be unstable. Insufficient power bypass capacitors can also cause them to be restless. Finally, the input and output itself may oscillate into a single-port system. Some common causes of oscillation and corresponding countermeasures are discussed in this paper.

Some basic principles

Figure 1a shows a block diagram of a non-rail-to-rail amplifier. The input control GM module, the GM module to drive the gain node, and finally buffered output. The compensating capacitor cc is the main frequency response element. If there is a grounding pin, the CC loop should be connected to the ground. However, the general op Amp has no ground, and the capacitance current can only be returned to one or two power terminals.

Figure 1a: A typical non-rail-to-rail op amp topology.

Figure 1b is a block diagram of the simplest amplifier that supports rail-to-rail output. The output current of the input GM module is divided into two drive currents to two output transistors by a "current coupler". The frequency response is mainly determined by the two CC/2 capacitors that are in a parallel state. The above two topologies describe the vast majority of op-amp using external feedback.

Figure 1b: A typical rail-to-rail op amp topology.

Figure 1c shows the frequency response of an ideal amplifier, although they differ in electrical structure but have similar behavior. The unity-Gain bandwidth product frequency gbf=gm/(2p cc) is provided by the single-pole compensation circuit formed by the GM and Cc. The phase delay of these amplifiers is reduced from -180° to -270° near Gbf/avol, where the Avol is an open-loop amplifier DC gain. For frequencies far above this low frequency, the phase is maintained at -270°. This is known as the "main pole compensation", where the CC pole dominates the response and hides the various frequency limits of the active circuit.

Figure 1c: Idealized frequency response of op amp.

Figure 2 shows the open-loop gain and phase response of the LTC6268 amplifier in relation to the frequency. This is a very compact 500MHz amplifier that supports rail-to-rail output, and only 3fA bias current is an excellent example of the behavior of a real amplifier. The -90° phase delay of the main compensation circuit starts at approximately 0.1MHz and reaches -270° at about 8MHz, but above 30MHz will cross the -270°. In practical applications, due to the additional gain stage and output stage circuitry, all amplifiers have high-frequency phase delay in addition to the basic primary compensation delay. The typical additional phase delay starts at approximately GBF/10.

Figure 2:ltc6268 The relationship between the gain and the phase and the frequency.

In short, the key to stability with feedback is the loop gain and phase, or avol times the feedback factor, or the loop gain. If we connect the LTC6268 in the unity gain configuration, then 100% of the output voltage will be fed back. At very low frequencies, the output is a negative input inverting, or -180° phase delay. The compensation circuitry increases the -90° delay through the amplifier, allowing the negative input to the output to have a -270° delay. Oscillation occurs when the loop phase delay increases to ±360° or multiples of it and the loop gain is at least 1v/v or 0dB. The phase margin measures how far the phase delay is from 360° when the gain is 1v/v or 0dB. Figure 2 shows that the phase margin at 130MHz is approximately 70° (10pF red curve). This is a very healthy number, and the phase allowance as low as 35° may be available.

Another topic that is less discussed is the gain margin, although it is as important as the parameter. When the phase margin at some high-frequency points is zero, the amplifier oscillates if the gain is at least 1v/v or 0dB. As shown in 2, when the phase is reduced to 0 (or a multiple of 360°, or the -180° shown in the figure), the gain around 1GHz is approximately -24db. This is a very small gain. Oscillation does not occur at this frequency point. In practice, a gain margin of at least 4dB is generally required.

non-fully compensated amplifiers (decompensated amplifiers)

Although the LTEC6268 is stable at unity gain, some op amp is intentionally unstable. The design tradeoff provides higher slew rate, wider GBF, and lower input noise than the unity gain compensation method by designing the amplifier compensation circuitry to stabilize only at higher closed-loop gain. Figure 3 shows the Open-loop gain and phase of the lt6230-10. The amplifier is mainly used for feedback gain of 10 or higher, so the feedback network will attenuate at least 10 times times the output signal. With this feedback network, we look for the frequency at which the open-loop gain is 10v/v or 20dB, and we find that the phase margin at 50MHz is 58° (±5 v power supply). In unity gain, the phase margin is only about 0 °, and the amplifier oscillates.

Figure 3:lt6230-10 the relationship between gain and phase and frequency.

It is observed that all amplifiers will be more stable when the closed-loop gain is higher than the minimum stable gain. Even a 1.5 gain can make the amplifier with unity-gain stability much more stable.

Feedback Network

On this topic, the feedback network itself can also cause oscillations. Note in Figure 4 we put a parasitic capacitance in parallel with the feedback voltage divider resistor. This is unavoidable. Each of the components on the board has a capacitance of about 0.5pF to the ground, along with the capacitance of the wire. In practical applications, the node has at least 2pF of capacitance, and the capacitance per inch of the line is about 2pF. Therefore, it is easy to accumulate 5pF parasitic capacitance. Consider LTC6268 to provide +2 gain. To conserve power, we set the RF and RG values to a fairly high 10kW. When Cpar= 4pF, this feedback network is in 1/(2p*rf| | Rg*cpar) or 8MHz at a pole.

Figure 4: Load the parasitic capacitance of the feedback network.

Using the fact that the feedback network phase delay is –atan (F/8mhz), we can estimate that the loop 360° delay will occur at about 35MHz, when the amplifier's delay is -261°, and the feedback network delay is -79°. At this phase and frequency point, the amplifier still has a gain of 22dB, while the voltage divider gain is the voltage divider resistor gain = 0.1114 or-19db. The amplifier's 22dB gain multiply the feedback network -19db gain can be obtained at 0° phase of the loop gain is +3db, the circuit will oscillate. Therefore, it is necessary to reduce the value of the feedback resistor acting together with the parasitic capacitance so that the feedback pole is away from the loop's unity gain frequency. The ratio of Poles to GBF is better than 6 times times.

The OP amp input itself may be very capacitive, simulating cpar. In particular, low-noise and low-vos amplifiers have large input transistors whose input capacitance is larger than other amplifiers, and their feedback networks are loaded. You need to check the data sheet to see how much capacitance is in parallel with the Cpar. Fortunately, the LT6268 is only 0.45pF, which is a small value for this low-noise amplifier. The circuit with parasitic parameters can be simulated with the Lilterhon model running on the free LTSpice.

Figure 5 shows a way to make the voltage divider more tolerant of capacitance. Figure 5a shows the phase-in amplifier circuitry after Rin. Assuming that VIN is a low-impedance source (<in), Rin will effectively attenuate the feedback signal without changing the closed-loop gain. Rin will also reduce the voltage divider impedance, improve the feedback pole frequency, and is expected to exceed GBF. The loop bandwidth is reduced by Rin, and the input offset and noise are amplified by Rin.

Figure 5a: A method to reduce the cpar effect, and an increase in the phase-in amplifier circuit of Rin.

Figure 5b shows the reversed-phase configuration. The RG also performs loop attenuation without changing the closed-loop gain. In this case, the input impedance does not change due to "Rg", but the noise, offset, and bandwidth can become worse.

Figure 5b: A method for reducing the cpar effect, and a reversed-phase configuration.

Figure 5c shows the preferred method for compensating the Cpar in the same-phase amplifier. If we set cf* Rf = Cpar * Rg, we have a "compensated attenuator" and the feedback divider has the same attenuation at all frequency points, which solves the cpar problem. The mismatch of the product will cause a "bump" in the amplifier's pass band, resulting in a "skeleton" in the response, i.e. the low-frequency response is flat, but changed to another platform around f = 1/2p* Cpar * RG. Figure 5d shows the Cpar equivalent compensation circuit for the inverting amplifier. The frequency response needs to be analyzed to find the correct CF, and the amplifier bandwidth is part of the analysis.

Figure 5c: The method of reducing the cpar effect and the optimal method of compensating the Cpar in the same-phase amplifier.

Figure 5d: A method for reducing the cpar effect and an equivalent cpar compensation circuit for an inverting amplifier.

Some comments on the current feedback amplifier (CFA) are listed here in order. If the amplifier in Figure 5a is a CFA, then "Rin" does not have much effect on modifying the frequency response because the negative input has a very small impedance and is a full copy of the positive input. The noise is somewhat poor, and additional negative input bias current vos/rin occurs. Similarly, the frequency response of the circuit shown in Figure 5b will not be changed by "Rg". The inverting input is not just a virtual ground, it has a really low impedance to the ground, and has tolerated cpar (inverting mode only!). )。 The DC error is similar to the error shown in Figure 5a. Figures 5c and 5d are the first choice for voltage input op amp, but CFA cannot tolerate direct feedback capacitance without oscillation.

Load issues

Just as the feedback capacitor may erode the phase margin, it also loads the capacitance. Figure 6 shows the relationship of the LTC6268 output impedance to the frequency under some gain setting conditions. Note that the unit-gain output impedance is lower than the higher gain impedance. Full feedback allows the open-loop gain to reduce the intrinsic output impedance of the amplifier. In this way, the output impedance of the gain of 10 in Figure 6 is generally higher than 10 times times the unit gain result. The feedback attenuator reduces the loop gain to a value of 1/10, otherwise the closed-loop output impedance is reduced. The open-loop output impedance is approximately 30W, which is easily visible from the flat portion of the gain 100 curve high frequency zone. In this area from approximately the gain band frequency/100 to the gain bandwidth frequency, there is essentially not enough loop gain to reduce the open-loop output impedance.

Figure 6:ltc6268 the relationship between output impedance and frequency under three gain conditions.

The capacitive load will cause phase and amplitude delay along with the open-loop output impedance. For example, the 50pF load and the LTC6268 30ω output impedance together will generate another pole at the 106MHz point, when the output has -45° phase delay and -3db attenuation. At this frequency point, the amplifier has a -295° phase and a gain of 10dB. Given the unity gain feedback, it is not entirely possible to oscillate because the phase does not cause the delay to reach ±360° (at 106MHz). At 150MHz points, however, the amplifier has a 305° delay and a gain of 5dB. The phase of the output pole is –atan (150mhz/106mhz) = -55°, and the gain is = 0.577 or -4.8db. By multiplying the loop gain, you can get 360° and +0.2db gain and oscillate again. The 50pF appears to be the minimum load capacitance that forces the LTC6268 to oscillate.

The most common way to prevent oscillation from load capacitance is to concatenate a small value resistor after the feedback connection. The 10ω to 50ω resistance limits the possible phase delay caused by the capacitive load and isolates the amplifier from the low capacitance impedance at high speeds. Disadvantages include DC and low frequency errors depending on the load resistance characteristics, limited frequency response on the capacitive load, and signal distortion if the load capacitance changes with the voltage.

Oscillations caused by load capacitance can generally be prevented by increasing the closed-loop gain of the amplifier. Running the amplifier with a higher closed-loop gain means that the feedback attenuator also attenuates the loop gain of the frequency point at which the loop phase is ±360°. For example, if we use a LTC6268 with a closed-loop gain of +10, we can see that the amplifier has a gain of 10v/v or 20dB at 40MHz, and the phase delay is 285 °. To excite the oscillation, we need an output pole, which causes a delay of additional 75°. We can get this output pole by using -75°=-atan (40mhz/fpole) →fpole = 10.6MHz. This pole frequency is derived from the load capacitance of 500pF and the output impedance of the 30pω.

The output pole gain is 0.026. When the open loop gain is not loaded at 10 o'clock, the loop gain at the oscillation frequency point is 0.26, so this time there is no oscillation, at least not the oscillation caused by the simple output pole. This allows us to increase the tolerable load capacitance from 50pF to 500pF by increasing the closed-loop gain.

The non-terminating transmission lines are also very bad loads because they present a wildly repetitive impedance and phase change (see the impedance of the 9-inch cable not terminated in Figure 7). If the amplifier is able to drive the cable safely at a low frequency resonant point, it is likely to oscillate at a higher frequency point as its own phase margin decreases. If the cable must be connected without any connection, then the "post-match" resistor in series with the output can isolate the basic impedance variation of the cable. In addition, even if the instantaneous reflection from the end of the cable is returned to the amplifier, the matched resistor can absorb the energy correctly if its value matches the cable characteristic impedance. If the post-match resistor does not match the cable impedance, some energy is reflected back from the amplifier and terminal to the end of the non-terminating termination. When the energy reaches the end, it returns to the amplifier again efficiently, so there is a series of pulses that bounce back and forth, but each bounce decreases.

Figure 7: Impedance and phase of the coaxial cable is not terminated.

Figure 8 shows a more complete output impedance model. One of the rout items is 30ω, as discussed in LTC6268, and we have added lout. This is a combination of the physical inductance and the electrical equivalent inductance. Physical packages, binding lines and external inductors can be increased by 5 to 15nH, and the smaller the package, the smaller the inductance. In addition, for any amplifier, there is an electrically generated 20-70nh range of inductance, especially bipolar devices. The parasitic base resistance of the output transistor is converted by the device's finite ft to inductance.

Figure 8: Inductance portion of the amplifier's output impedance.

The danger is that lout may interact with CL and form a series resonant tuning circuit where the impedance of the circuit may fall into the loop and there is no more phase delay within the potential oscillation rout will not be able to drive the level. For example, set lout = 60nH and cl = 50pF. Resonant frequency is

Resonant frequency 92MHz, completely in the LTC6268 pass band. This series resonant circuit effectively loads the output of the resonant point and substantially alters the loop phase near the resonant point. Unfortunately, lout is not generally mentioned in the amplifier data sheet, but it can sometimes be seen in an open-loop output impedance diagram. In general, this effect is not important for amplifiers with bandwidth below 50MHz.

Figure 9 shows a solution. Rsnub and Csnub form the so-called "damper", which aims to reduce the Q value of the resonant circuit so that the amplifier output does not form a very low resonant impedance. Rsnub generally at the resonance point of CL reactance value, in this case is-j35ω, so that the output resonant circuit of the Q value to pull down to about 1. CSNUB adjusted to the output resonant frequency point completely inserted into the RSNUB, that is Csnub reactance component <snub =10* CL is very practical. The CSNUB can unload the amplifier at mid-low frequency, especially when DC. If the csnub is very large, then the amplifier will increase the load due to RSNUB in the intermediate frequency or low frequency, and gain accuracy, closed-loop bandwidth and distortion may become worse. In any case, with only a small amount of adjustment, this damper is very useful for improving the reactance load, but it must be adjusted by experience.

Figure 9: Using the output damper.

The negative input of the current feedback amplifier is actually a buffer output, as well as the series characteristics shown in Figure 8. So it can oscillate itself in the cpar, just like the output. You should try to reduce the cpar and any associated inductors. Unfortunately, the damper on the negative input modifies the relationship between the closed-loop gain and the frequency, so it is not very useful.

Strange impedance.

Many amplifiers present an input impedance anomaly at high frequencies. This is especially true for amplifiers with two input transistors in series, just like the Darlington tube. Many amplifiers have a NPN/PNP transistor pair at the input, and their frequency behavior is very similar to the Darlington tube. At a frequency point much larger than GBF, the real part of the input impedance becomes negative. The reactance source impedance is resonant with the input capacitance and the circuit board capacitance, and the negative real component increases the oscillation. This can also allow oscillation at many repetitive frequency points when the cable is never terminated. If the input is inevitably using a long inductance line, it can be segmented with a series of energy-absorbing resistors, or a medium-impedance damper (about 300 Ω) is installed on the amplifier input foot.

Power supply

The last oscillation source to consider is the Power bypass capacitor. Figure 10 shows a portion of the output circuit. The lvs+ and lvs-are the necessary inductors for the package, IC binding line, the physical length of the bypass capacitor, as well as the inductance properties of any conductor, and the circuit board's line inductance in series. Also included is an external inductor that connects the local bypass capacitor to the rest of the power bus, if not the power supply layer. Although 3-10NH does not look much, it also has 3.8 to j12ω at 200MHz. If the output transistor transmits a large high-frequency output current, a pressure drop will be generated on the power inductor.

Figure 10: Power bypass capacitance details.

The rest of the amplifier requires a quiet, uninterrupted power supply, because it cannot suppress power on a certain frequency. In Figure 11 we can see the power rejection ratio (PSRR) of the LTC6268 at different frequencies. Because the compensation capacitor is related to the power supply in all non-grounded pins, they will couple the power supply noise into the amplifier, and the GM must be able to eliminate the noise. Because of the compensation, PSRR can reduce the F/F, and after 130MHz power supply rejection actually becomes gain.

Figure 11:ltc6268 The relationship between the power supply rejection ratio and the frequency.

Since PSRR is shown as gain at 200MHz, the output current interferes with the supply voltage within the LV inductor and becomes a powerful amplifier signal by PSRR amplification, which drives the output current, forms an internal supply signal, and causes the amplifier to oscillate. This is why all amplifier power supplies must be carefully used with low inductance of the route and component bypass. In addition, the power bypass capacitor must be much larger than any load capacitance.

If we consider the frequency around 500MHz, then the 3-10NH will become j9.4ω to j31.4ω. This high value is sufficient to allow the output transistor to oscillate independently within its inductance and IC element capacitance, especially if the transistor GM and the bandwidth increase form a larger output current. Because today's semiconductor manufacturing process uses a very high transistor bandwidth, special attention is needed, at least at large output currents.

Summary of this article

In summary, the designer needs to consider the parasitic capacitance and inductance associated with each OP amp terminal and the load's natural characteristics. Generally designed amplifiers are very stable in a nominal environment, but each application needs to be analyzed by itself.

Is your op-amp going to vibrate?