Latency of next-generation SSD controller based on low-density Inspection

Latency of next-generation SSD controller based on low-density Inspection

Author: Stephen Bates

Latency Variability

In the previous blog, I talked about how the Error Correction Code (ECCS) in the enterprise-level SSD controller is being converted to Low-Density Parity Check (Low-Density Parity Check. This article also implies that this conversion will have a profound impact on the latency in the next-generation SSD controller. This article will further elaborate on this.

In SSD, the latency related to the low-frequency and low-frequency inspection (ECC) is mainly due to three reasons:

1. The process of encoding a low-density byoc

2. The first time the data is read on the nand flash memory.

3. Check the decoding process of the non-checksum code related to subsequent Data Reading on the nand flash memory.

In high-performance SSDS, latency related to the first source is negligible. They are usually hidden by using Write-back caching and other technologies, and are not known to users. However, latency related to the second and third sources cannot be hidden from users.

Next, we will continue to analyze the latency generated by the second and third sources. The following table shows several major latency components related to random read on an enterprise-level SSD. Interestingly, only the t_read and t_low-QPS items have variability, and the t_read variability is much larger than that of t_low-QPS (60us vs. 19us ).

Project	Time(US)	Category(US)	Maximum Value(US)	Description
Flash read time (t_read)	60	80	120	Common and representative values of mlc nand flash memory
Conversion time (t_trans)	10.2	10.2	10.2	Assume that the operation is 4 kb read and the speed is 400mt/s onfi/toggle.
Time of decoding (t_low-income ratio)	1	4	20	Assume that the latency of each iteration of the decoder is 1 us. At least one iteration, usually four iterations, up to 20.

The change of the flash memory read time (t_read) depends on the page index (some pages are essentially faster than other pages); the rest are randomly changed with the single read of the same page. This indicator remains the same for SSDS based on low-density and BCH.

The change in the time of decoding of the Low-Density checksum encoding is required for decoding data from the flash memory.IterationNumber of times. The decoder uses iterative decoding. The number of iterations at the beginning of decoding is generally unknown. You can set an upper limit for the number of iterations to limit the number of t_low-frequency pairs when decoding fails.

The number of iterations in the decoding process depends on the parameters of the encoding and the number of errors in the read operation segments on the nand flash memory. It is helpful for us to think further, this means that you can change the t_parity check by controlling any or both of the preceding two metrics.

It is shown that the choice of the Low-density and low-density parameters can affect and change the t_low-density and low-density parameters.

When the number of errors on the nand flash memory is very low, t_low-density inspection is the same for ldpc1 and ldpc2. However, as the number of errors increases, ldpc2 starts to show a low latency (t_low-density inspection) compared with ldpc1 ). In SSD, you can use either of the following methods:

1.Static Parity Check Configuration-To minimize latency, you can choose ldpc2 in SSD.

2.Dynamic checksum Configuration-If the SSD supports dynamic configuration, you can select ldpc1 when the NAND error rate is low (that is, at the beginning of the SSD lifecycle), and then switch to ldpc2 as the ssd nand flash memory ages.

It is worth noting that any given SSD controller may have more than two types of low-income inspection codes. In this case, you can flexibly compromise between the parameters of the low-income inspection code and the latency related to t_read.

It would be even better if the initial decoding of the Low-Density Parity Check fails. In this case, the next step is to go back to the nand flash memory itself and start to work towards the soft-decision-making of low-density decoding. The next article in this series of blog posts will discuss this issue.