Launch edge and latch edge delay

This article turns from http://www.cnblogs.com/inet2012/archive/2012/03/07/2384149.html

Launch Edge and latch edge respectively refers to the beginning and end of a path, only a reference time, in itself there is no meaning, latch_edge-launch_edge only meaningful. 1. Background

The premise of static time series analysis is that the designer makes the request first, then the timing analysis tool will analyze according to the specific time series model and give the correct time-series report.

For static timing analysis, the main purpose is to improve the system operating frequency and increase the stability of the system. For many digital circuit designs, it is important to increase the operating frequency because high operating frequencies mean high processing power. Additional constraints allow you to control the synthesis, mapping, layout, and routing of logic to reduce logic and cabling delays, thereby increasing the operating frequency. 2. Theoretical analysis 2.1 Fixed parameters launch Edge, latch edge, TSU, Th, TCO concept 2.1.1 Launch edge

Timing analysis starting point (Launch edge): The clock edge of the first-level register data change, which is also the starting point for static timing analysis. 2.1.2 Latch Edge

Timing Analysis Endpoint (latch edge): The clock edge of the data latch, which is also the end point of the static timing analysis. 2.1.3 Clock Setup Time (TSU)

Settling Time (TSU): Refers to the time required for the data to stabilize before the clock arrives, and if the established time does not meet the requirements then the data will not be able to rise along the clock in a stable break-in trigger. 3.2 is shown below:

2.1.4 Clock hold Time (TH)

Hold Time (TH): Refers to the time the data is stable, and if the retention time is not satisfied, then the data can not be stable into the trigger. Hold time 3.3 as shown:

2.1.5 Clock-to-output Delay (TCO)

Data output delay (TCO): This time refers to the minimum time interval between the data from the input to the output when the clock is effective along the change. 2.2 Clock Skew

Clocking skew (clock skew): Refers to the time offset of a clock source reaching two different register clock ends, as shown in 3.4:

The clock skew is calculated as follows:

Tskew = TCLK2-TCLK1 (Formula 2-1) 2.2 Data arrival time

Data arrival time: The time required for the input data to arrive after the valid clock. Mainly divided into three parts: clock arrival Register Time (TCLK1), register output delay (TCO) and data transmission delay (TDATA), 3.5 shows

The data arrival time calculation formula is as follows:

Data Arrival time = Launch Edge + Tclk1 +tco + tdata (Formula 2-2) 2.3 Clock Arrival time

Clock arrival time: The time the clock takes to reach the latch register clock input from the latch edge is the clock arrival time, shown in 3.6

Figure 3.6 Clock Arrival time

The clock arrival time calculation formula is as follows:

Clock Arrival time = Lacth Edge + Tclk2 (Formula 2-3) 2.4 Data Required time (setup/hold)

Data Required time: The data must be stable between the settling time and the hold time of the clock latch, and the time required to reach this steady state from the Origin clock point is the data demand time. 3.7 is shown below:

Figure 3.7 Data Demand time

The data demand time calculation formula is as follows:

Data Required time = Clock arrival Time-tsu (Equation 2-4)

(hold) The data demand time formula is calculated as follows:

Data Required time = Clock arrival time + Th (Formula 2-5) 2.5 Setup slack

Set up time allowance (Setup slack): When the data demand time is greater than the data arrival time, say time surplus, Slack is a designation that indicates whether the design satisfies the timing.

Figure 3.8 Settling the time allowance

As shown in 3.8, the calculation formula for settling the time allowance is as follows:

Setup slack = Data Required time-data arrival time (Equation 2-6)

It is known from the formula that the positive slack indicates that the data demand time is greater than the data arrival time, satisfies the timing (the margin of the timing), the negative slack indicates that the data demand time is less than the data arrival time, does not meet the timing (the lack of timing). 3.1.7 Clock Minimum cycle

Clock minimum period: the maximum frequency at which the system clock can run.

1. When the data demand time is greater than the data arrival time, the clock has a margin;

2. When the data demand time is less than the data arrival time, the timing requirement is not satisfied, the register undergoes metastable state or the data is not obtained correctly;

3. When the data demand time equals the data arrival time, this is the minimum clock run frequency, just to meet the timing.

From the above three points can be obtained the minimum clock period is the data arrival time equals the data demand time, the operation formula is as follows:

Data Required time = data arrival time

Additional: Graphical Setup and hold Slack

The definition and calculation method of Setup and hold slack can be clearly seen from the above image:

Setup Slack=latch edge+tclk2-tsu-(Launch Edge+tclk1+tco+tdata)

= (latch Edge-lanuch edge) + (TCLK2-TCLK1)-(Tsu+tco+tdata)

For the tool's default single cycle, latch Edge-lanuch edge=t, if the skew,tclk2-tclk1=0 of the clock is not taken into account, the upper formula can be expressed as:

Setup slack=t-(Tsu+tco+tdata), which is the reason why the delay between the source register and the destination register is not too long, the longer the delay, the smaller the slack.

Hold Slack=data arrival Time–data required Time
= (Launch edge + TCLK1 + Tco + tdata) – (latch edge + TCLK2 + Th)
= (Launch Edge–latch Edge) – (TCLK2–TCLK1) + (Tco + tdata + Th)

Note that the launch edge in the above is the next launch edge, which is the latch edge, so launch Edge–latch edge=0, if the skew,tclk2-tclk1=0 of the clock is not considered, the formula can be expressed as:

Hold Slack=tco + tdata–th, which is why the delay between the source register and the destination register cannot be too short, the time is too short, the slack smaller. Setup slack calculation

Hold slack calculation

Launch edge and latch edge delay