7 Operating modes for 1.ARM system CPUs
(1) User mode (USR): ARM processor normal program execution status.
(2) Fast interrupt mode (FIQ): For high-speed data transmission or channel processing.
(3) Interrupt mode (IRQ): Used for general interrupt handling.
(4) Management mode (SVC): The protection mode used by the operating system.
(5) Data access termination mode (ABT): Enter this mode when data or instruction prefetching is terminated, and can be used for virtual storage and storage protection.
(6) System mode (SYS): Runs a privileged operating system task.
(7) Undefined instruction Abort mode (und): Enter this mode when undefined instruction is executed, which can be used to support software emulation of hardware coprocessor.
The software can be used to switch mode, or the occurrence of various types of interrupts, abnormal when the CPU automatically into the corresponding mode. In addition to user mode, 6 modes of operation are in privileged mode, most programs run in user mode and enter privileged mode to handle interrupts, exceptions, or access to protected system resources.
Register of 2.arm920t
The ARM920T has 31 general-purpose 32-bit registers and 6 program status registers, which are 37 registers divided into 7 groups that use the set of registers when entering a working mode. Some registers, which have their own copy in different operating modes, will be used when switching to another mode of operation: These registers are called backup registers. You can see that the FIQ mode has the most backup registers, which is to increase the response speed of the Fiq and reduce the time it takes to save the register value.
CPSR is the same register in seven modes, so you can modify the values inside to convert to different operating modes. R0~R15 can be accessed directly, except for R15, which are universal registers that can be used to save data or to save addresses. R13~r15 slightly Special: R13 is also known as the stack pointer register SP, usually used to hold the stack pointer, R14 is also known as the program Connection register, when the BL subroutine call instruction is executed, R14 in the R15 (program counter PC) backup, and when an interrupt or an exception, the corresponding R14_SVC , R14_irq, R14_fiq, R14_abt, or R14_und to save the return value of R15; R15 is also known as the program counter PC.
3.CPSR Registers
The CPSR includes the following status bits:
(1) T-bit: The CPU is in the thumb state when set, otherwise it is in arm state.
(2) Interrupt prohibition bit: I and F bits belong to the interrupt stop bit. When they are set, IRQ interrupts, Fiq interrupts are disabled respectively.
(3) Working mode bit: Indicates the current operating mode of the CPU, can change these bits, so that the CPU into the specified mode of operation.
4.SPSR Registers
The SPSR register, the program state Save Register, is a backup register that saves the CPSR register in 5 modes except system and user mode. When an exception occurs, it switches into the appropriate mode of operation, when the ARM920T CPU will automatically do the following.
(1) in the abnormal operating mode of the connection register R14 Save the previous mode of operation of the next, the address of the instruction to be executed. For ARM status, this value is the current PC value plus 4 or plus 8.
(2) Copy the value of the CPSR to the SPSR of the exception mode.
(3) The working mode of the CPSR is set to the working mode of the abnormal.
(4) The PC value equals the address of the exception mode in the exception vector table, that is, jump to execute the corresponding instruction in the exception vector table.
Conversely, the following things need to be done through the software when exiting from the abnormal working mode to the previous mode of operation.
(1) Before entering the abnormal mode of operation, the connection register saves a command address of the previous mode of operation, subtracting an appropriate value from it and assigning it to the PC register.
(2) Copy the value of SPSR back to CPSR.
As can be seen from the table, when entering and exiting the exception, the PC's calculation method will be calculated according to different patterns, mainly divided into 3 categories (in the table (1) (2) (3) that the pattern belongs to the classification):
(1) The PC value is the address of these instructions: SWI, undefined instruction, command failed at prefetch. This instruction has been executed and the address of the next instruction is pc+4.
(2) The PC value is the address of these instructions: instructions that were interrupted and not executed before entering the fast interrupt, interrupt mode. This instruction is interrupted, so the next instruction is the one that the PC is currently pointing to.
(3) The PC value is the address of these directives: load/Store instructions (LDR, STR, LDM, and STM) that result in data access termination. These special instructions, pipelining technology will cause the next few instructions are a copy of this instruction, so the directive is equivalent to not execute successfully, the following instruction is the current point of the PC instructions.
Note: pipelining technology causes the value of the PC to be the address of the currently executed instruction, but the instruction that has been taken by the command will continue to execute, interrupt, and so on, just take instructions, the instructions in the pipeline will continue to execute.
Learn to drive 17--arm working mode and ARM9 Register
