Learning PLL with lpc2103

I haven't come to blog for a long time. I have been busy with the exam, but everything is over. Now I can continue to do what I want to do. Today, I went to the lab to continue playing arm and learned the 2103 PLL part. In general, it is relatively simple. Of course, I am not very clear about the specific implementation of the PLL hardware. I didn't learn well at the beginning ..

PLL Overview:

The original input clock frequency range of the PLL is only 10 MHz ~ 25 MHz, and then multiply to the range of 10 MHz ~ Through A oscillator (CCO ~ 70 MHz. The frequency multiplier can be an integer between 1 and 32, but there are not so many, because it is related to the specific maximum operating frequency of the lpc2103. The maximum frequency is 70 MHz. The cCo operation frequency is 156mhz ~ 320 MHz. Therefore, there is an additional divider inside the PLL to keep the CCO within the frequency range when the PLL provides the required output frequency. The output divider can be set to 2, 4, 8, or 16 to generate an output clock. Demonstrate the internal logic principle of the PLL.

PLL activation is controlled by pllcon registers, and the pllcfg registers control the values of the PLL multiplier and divider. Because all the operations on the chip depend on the PLL (including the watchdog), if PPL is incorrect, it will cause subsequent execution errors. Therefore, we need to protect it, and the protection operation is similar to the feed sequence that operates the watchdog timer. The PLL is shut down and bypassed when the chip is reset and enters power-down mode. The Application of PLL can only be implemented through software. The program must wait for the PLL to be locked after it is configured and activated, and then connect to the PLL as a clock source.

Below are the related registers of the PLL. There are only four registers.

1. Select the operating frequency of the processor to be operated (cclk) and set it according to the overall requirements of the processor. The clock frequency of peripheral devices can be lower than the processor frequency.

2. Select the oscillator frequency (fosc ). Cclk must be an integer multiple of fosc.

3. Calculate the m value to match the msel bit. M = cclk/fosc. The value range of M is 1 ~ 32, in pllcfg, the write msel value is M-1.

4. Select the P value to configure the psel bit so that fcco is within the defined frequency limit. P must be one of 1, 2, 4, or 8. The values of psel written to ppcfg are listed in the following table.

There are two methods to perform the PLL operation.

1. Query Method

1. pllcon = 1. Before you set the PLL, You need to enable the PLL, but cannot connect to the PLL.

2. Set the P and M values (pllcfg)

3. Send the PLL feed sequence.

4. Wait for the PLL to lock -- pllstat.10 = 1.

5. pllcon = 3. Connect the PLL after setting P and M.

6. Send the PLL feed sequence and write the values of P and M to the hardware.

Second, interrupt mode

1. pllcon = 1. Before you set the PLL, You need to enable the PLL, but cannot connect to the PLL.

2. Set the P and M values (pllcfg)

3. Send the PLL feed sequence.

PLL interrupt service program:

4. pllcon = 3. Connect the PLL after setting P and M.

5. Send the PLL feed sequence and write the values of P and M to the hardware.

6. Disable PLL interruption and return.

 

The above section is about the PLL. See easyarm2103

 

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