Learning logs (Time Series Circuit) using)

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In my opinion, no matter what language you want to learn, you must practice it. In fact, only by constantly polishing and practicing can we truly get knowledge and experience from mistakes. · As mentioned in the previous blog post, we can write a simple Time Series Circuit today and use cyclic counting.

 
Module count (CLK, reset, data); input CLK; input reset; output data; Reg [3: 0] DATA = 4'b0; always @ (posedge CLK or negedge reset) if (reset = 0) Data <= 4'b0; else data <= Data + 1'b1; endmodule
 

The aboveCodeIt is relatively simple to count data. Below we can write a testbench code for this module,

Module count_t; Reg CLK; Reg reset; wire [3: 0] data; count t (CLK, reset, data); initial CLK = 0; always forever #5 CLK = ~ CLK; initial begin #20 reset = 1 ;# 200 $ finish; end initial $ Monitor ("Data = % d \ n", data); endmodule
 

From the test code, the content is also very simple. There are three main signals: CLK, reset, and data. The CLK signal is flipped once by 5ns, And the reset signal is set to a high level after 20ns, and the data signal starts to count cyclically. After the data reaches 15, it is restored to 0. If you are interested, you can see what dataflow and wave are processing.