Linux Kernel 0.11 head

The Bootsect and setup assembly uses Intel's assembler style, while in the head, it is now in the 32-bit protection mode, the assembly of the AT-T assembly language, the compiler will of course become the corresponding compiler and connector.

Concept:

① a detailed description of the interrupt descriptor, see: http://blog.csdn.net/fwqcuc/article/details/5855460

② about the control register (CR0,CR1,CR2,CR3): http://blog.csdn.net/sunnybeike/article/details/6781353

The control register (CR0,CR1,CR2,CR3) is used to control and determine the operating mode of the processor and the characteristics of the current execution of the task. They are all 32-bit control registers.

CR1: is reserved for future processors to use, in 80386 cannot use CR1, otherwise it will cause invalid instruction operation exception.

CR0: Includes a control bit that indicates how the processor works, contains a control bit that enables and disables the paging management mechanism, and contains control bits that control the operation of the floating-point coprocessor.

CR2, CR3: Used by the paging management mechanism.

Among them, bits 5-bit 30 in CR0 and bits 0 to 11 in CR3 are reserved bits, which cannot be random values and must be 0. The lower 16 bits of CR0 are equivalent to 80286 of the machine state word MSW.

　　A detailed introduction

Protection control bits in the 1.CR0

The bit 0 in the control register CR0 is labeled with a PE, bit 31 is marked with a PG, and these two bits control the operation of the segmentation and paging management mechanisms, so they are referred to as protection control bits. PE control subsection management mechanism. Pe=0, the processor runs in real mode; pe=1, the processor runs in a protected mode. PG controls the paging management mechanism. Pg=0, the paging management mechanism is disabled, and the linear address generated by the segmentation management mechanism is used directly as the physical address, and the paging management mechanism is enabled, and the linear address is converted to the physical address by the paging management mechanism at this time. Pg=1. It can be concluded that the PE and PG flags are set if the paging mechanism is to be enabled. Because paging is enabled only in protected mode, there are four combinations of two bits, 0 and 1, respectively, but only three are valid. Pe=0 and pg=1 are invalid combinations, so loading a CR0 register with a value of 1 and a PE of 0 will cause a generic protection exception.

2.CR0 co-processor control bit

The bit 1-bit 4 in the control register CR0 is marked as:

①MP (arithmetic existence bit)

②em (analog bit, used to select the protocol used to communicate with the coprocessor, indicating whether a 80386 or 80286 coprocessor is used in the system)

The EM bit controls whether the execution of a floating point instruction is performed by a software simulation or by hardware. When em=0, a hardware control floating point instruction is transmitted to the coprocessor; when Em=1, the floating point instruction is simulated by the software.

③ts (task switch bit)

TS bits are used to speed up task switching, which is achieved by the method of coprocessor switching if necessary. Each time a task is switched on, the processor puts TS 1. Ts=1, the floating point instruction will produce a device unavailable (DNA) exception. The MP bit controls whether the wait instruction produces a DNA abnormality when ts=1. Mp=1 and Ts=1, wait generates an exception; when mp=0, the wait instruction ignores the TS condition and does not produce an exception.

④et (Extension type bits), which control the operation of the floating-point coprocessor.

When the processor is reset, the ET bit is initialized to indicate the type of the digital coprocessor in the system. If there is a 80387 coprocessor in the system, then the ET position 1, if there is a 80287 coprocessor in the system, or there is no coprocessor, then the ET bit clear 0.
　　
When the system has just been power-up, the processor is reset to pe=0,pg=0 (that is, the real mode state) to allow the boot code to initialize these registers and data structures before enabling the staging and paging mechanisms. Use of this type of register is available under real mode.

3.cr2 and CR3

The control registers CR2 and CR3 are used by the paging management mechanism.
CR2 is used to report error messages when a page exception occurs. When a page exception occurs, the processor stores the linear address that caused the page exception in CR2. The page exception handler in the operating system can check the contents of the CR2 to find out which page in the linear address space is causing the exception.
The CR3 is used to hold the physical Address of page catalog table pages and is therefore called PDBR. Because the directory is page-aligned, only the high 20 bits are valid and the low 12 bits are reserved for more advanced processors to use. When a new value is loaded into the CR3, the low 12 bits must be 0, but when the value is taken from CR3, the low 12 bits are ignored. Each time the CR3 value is reset with the MOV instruction, the content of the paging mechanism cache is invalidated, and the paging mechanism can be pre-refreshed before the paging mechanism is enabled, that is, before the PG position 1. The CR3 register can be mounted even if the PG bit or PE bit of the CR0 register is 0 o'clock, as in real mode you can set the CR3 to initialize the paging mechanism. When the task is switched on, the CR3 is changed, but if the CR3 value in the new task is the same as the value CR3 in the original task, the processor does not refresh the paging cache so that it performs faster when the task shares the page table.

Linux Kernel 0.11 head