Linux kernel interrupt subsystem (i)--ARM GIC hardware

In a system, interrupts are an important part of the system can not always poll (polling) whether there is an event, the system efficiency is improved, and the control of the interruption is usually scattered in various places, different parts by different functions of the program, to do their own duties, with error , the system will work correctly. In the general system, the interrupt control is divided into three places: module, interrupt controller, processor, the module usually has registers can control whether interrupt function, interrupt trigger condition, etc., interrupt controller can manage the priority of the interrupt, and the processor that handles all interrupts has the register setting to respond interrupt.

1. Panorama

As the general interrupt controller in the ARM system is the GIC(Generic Interrupt Controller) , There are currently four versions, V1~V4 (V2 supports up to 8 arm core,v3/v4 to support more arm core, Mainly used for ARM64 system structure). Currently, the official ARM website can only be downloaded to version 2 of GIC architecture specification. where GIC-500 supports up to 128 CPU cores, it requires arm core to be a ARMV8 instruction set (for example, Cortex-a57), in accordance with GIC Architecture specification version 3. This article mainly describes the GIC-400, which is more suitable for embedded systems, in accordance with version 2 GIC architecture specification. GIC-400 is connected to one or more arm processor via an on-chip bus such as the AMBA (Advanced microcontroller bus Architecture). take a look at the function of the GIC in the System Panorama (Overview).

As can be seen from this diagram, GIC is a bridge between peripheral interrupts and CPUs , as well as a channel (with management) that interrupts the interconnection between CPUs, and it is responsible for detecting, managing , distribution interruption, you can do:

To enable or prohibit interruption;

Grouping interrupts into group 0 or group 1 (using FIQ in the security system , Group0 , Group1 used as a non-secure system, connecting IRQ );

A multi-core system distributes interrupts to different processors;

Set level trigger or Edge trigger mode (not equal to the trigger mode of peripheral);

Virtualization extensions;

ARM CPU External connection only 2 interrupts, one is IRQ , one is FIQ , the corresponding processing mode is the general interrupt ( IRQ ) processing mode and fast interrupt ( FIQ ) processing mode. So the GIC will end up with a 2 -line interrupt and a CPU docking.

2. Detailed design

Introduction to the overall impression, the following to introduce the detailed section, before the introduction, first understand  GIC  , gic  in Span style= "font-family: Arial" > broken type has 3 Type: sgi (software-generated interrupt) , ppi (private peripheral interrupt ) , spi (shared peripheral interrupt)

SGI: SGIs is generated by writing to the software generated Interrupt Register, Gicd_sgir. Each CPU interface can generate a maximum of SGIs, ID0-ID15, for each target processor. SGI is an interrupt that the software can trigger, with a uniform number of 0~15, for communication between the various cores.

PPI: A PPI is an interrupt, that's specific to a single processor. All PPI signals is Active-low level-sensitive. Table 2-3shows The PPIs that is available for each processor. Ppifor eachCoreThe private peripherals are interrupted, and the unified number is16-31, such as eachCPUThe local timer isArch Timerthe resulting interruption is throughPPIsent toCPU(Security is 29, non-security is 30).

SPI: SPIs is triggered by events generated on associated interrupt input lines. The GIC-400 can support up to 480 SPIs corresponding to the external irqs[479:0]signal. The number of SPIs available depends on the implemented configuration of the GIC-400. The permitted values is 0-480, in steps of 32. SPIs start at ID32. You can configure whether each SPI are edge-triggered on a rising edge or is Active-high level-sensitive. Tp.is the interrupt generated by the peripherals of the system, for eachCorepublic interrupts, uniformly numbered32~1019, such asGlobal Timer,UART,Gpiothe resulting interrupt.

Or look at the picture first:

as you can see, GIC can be clearly divided intotwo parts: Dispenser(distributor)and theCPU Interface(CPUINTERFACe). There are two kinds of CPU interface, one is the common processor interface, the other is the interface with the virtual machine. Virtual CPU interface is not described in detail in this article. Distributionthe device should be called the aggregator,ICin the back-end design,Layoutwill lead each module through theInterrupt Line (three interrupts mentioned above) mixedGICand then interrupts the mixed aggregation toCPUof theIRQand theFIQon the line, soCPUthere's a touch.

One distribute only one set, so the base address is only a, and Interface have multiple sets, because each CPU corresponds to a set of Interface. So strictly speaking, the number of the last line of the GIC should be the number of CPUs * 2, but usually designed to ensure that each CPU sees the interface base address is the same, the program see the base site is the same.

Each of these sub-interrupts enable, set the trigger mode, prioritize the order, distribute to which CPU these functions are responsible by distribute, the total interrupt enable, the maintenance of the State is responsible by Interface.

Distributor Overview

The main function of distributor is to detect the state of each interrupt source, control the behavior of each interrupt source, distribute the interrupt events generated by each interrupt source to the specified one or more CPUs On the interface. Although distributor can manage multiple interrupt source, it always takes the highest-priority interrupt request to the CPU interface. The Distributor control of interrupts includes:

(1) Interrupt the control of enable or disable. The Distributor control of interrupts is divided into two levels. One is the control of global interrupts (Gic_dist_ctrl). Once the global interrupt is disable, any interrupt event generated by the interrupt source will not be passed to the CPU interface. Another level is control over each interrupt source (gic_dist_enable_clear), disable a interrupt source causes the interrupt event not to be distributed to the CPU interface, but does not affect the distribution of other interrupt source-generated interrupt event.

(2) Control distributes the interrupt events with the highest current priority to one or a set of CPU interface. When an interrupt event is distributed to multiple CPU interface, the internal logic of the GIC should be guaranteed to assert only one CPU.

(3) Priority control.

(4) Interrupt property setting. For example, level-sensitive or edge-triggered?

(5) Setting of interrupt Group

Distributor can manage several interrupt source, which are identified by an ID, which we call interrupt ID.

CPU interface

CPU interface This block is primarily used to interface with the process. The main functions of the block include:

(a) Enable or disable CPU interface to the connected CPU Assert interrupt event. The interrupt signal line between the ARM,CPU interface block and the CPU is NIRQCPU and nfiqcpu. If an interrupt is disable, even distributor distributes an interrupt event to the CPU interface, but does not assert the specified NIRQ or NFIQ notification processor.

(b) ackowledging interruption. The processor will answer interrupts to the CPU interface block, and once the interrupt is answered, distributor will change the state of the interrupt from the pending state to active. If there are no subsequent pending interrupts, then the CPU interface will Deassert NIRQCPU and NFIQCPU signal lines. If a new interrupt is created in the process, the Distributor will change the state of the interrupt from the pending state to pending and active. At this point, the CPU interface will still maintain the asserted state of the NIRQ or Nfiq signal, which is the next interrupt to processor signal.

(c) Notification of interruption of processing. When interrupt handler finishes processing an interrupt, it notifies the GIC that the CPU has finished processing the interrupt by writing to the register of the CPU interface. Do this on the one hand is to inform distributor to change the interrupt state to deactive, on the other hand, can allow other pending interrupt to the CPU interface submit.

(d) Set priority mask. With the priority mask, you can mask off some of the less-prioritized interrupts that are not notified to the CPU.

(e) Setting the preemption strategy

(f) Select a notification with the highest priority when multiple interrupt events come together processor

different system settings interrupt affinity is different, such as the network server, always want to respond to network requests as soon as possible, Power consumption is not very important, so different interrupts can be assigned to different  CPU  to respond to interrupts as quickly as possible, while in the embedded system, the power consumption is very important, usually to bind the interrupt to  CPU0 , so other  CPU  When idle, can enter  IDLE  state, to save power, ARM CPU normal operation, only use the Arch timer, will not use the Global timer, that is, the system timer will not run. However, when the  cpu power is turned off, the CPU's Arch Timer is also turned off, so that when the CPU enters the idle state of power off, it must first switch its timer to the Global timer, so that when the next Timer arrives, if the CPU is not started , there will be a response to the Global Timer in the  cpu sent an SGI interrupt, there will be an interruption, other modules will be removed from the power state, if it is CPU0, also received an interruption, Other modules take it out of the power-off state, but at this point the interrupt is no longer SGI, but the interruption of the Global Timer.

usually  DISTRIBUTE  belongs to the system power domain, and interface CPU  Power domain, so every   CPU  Power back up (the system is constantly powered),   INTERFACE 

New initialization. In addition, if you want to keep the CPU in WFI State, you need to set the Interface GICC_CTLR The register is 0, otherwise the CPU exits from the WFI state.

Registers in safe and non-safe mode read the value is different, this does not mean that the security and non-security state, the same address of the register there is a backup (likeIRQand theFIQmode, some registers are backed up), but because of different registersbitdifferent properties, some of which belong to the security registerbitread in a non-secure state0, soCPUafter resetting, before switching to a non-secure system, set theGIC, or the security system cannot respond to interrupts, i.e. the security system cannot be used,CPUwill stop where the quiet rest, at this time to seeThe phenomenon is: the CPU in the WFI state, the system clock is also stopped, because the CPU Arch-timer is not responding, tick count will not change.

3. Interrupted processing process

the processing flow for interrupts is:Distributor will collect the interrupt, first cache, then the highest priority of the interrupt request sent to the CPU interface ,the CPU reads an interrupt, actually reads a register of interface , except that this register holds the interrupt number, when the state of the interrupt is pending Switch Active , CPU after processing is finished, write the interrupt number GIC of the Interface , Tell GIC after processing, this interruption can be cleaned up.

View how interrupts on the system are allocated on the CPU orders for situations and response times :

# cat/proc/interrupts

4. Registers

Reference:

Ddi0471b_gic400_r0p1_trm.pdf

IHI 0048B, ARM Generic Interrupt Controller Architecture specification, Ver 2.0.pdf

Http://www.wowotech.net/linux_kenrel/gic_driver.html

http://blog.csdn.net/velanjun/article/details/8757862

Http://www.ibm.com/developerworks/cn/linux/l-cn-linuxkernelint/index.html

Linux kernel interrupt subsystem (i)--ARM GIC hardware