Logical bank and chip capacity representation of SDRAM

1. Logical bank and Chip Width
After explaining the external form of the SDRAM, we should have a deep understanding of the internal structure of the SDRAM. The main concept here is the logical bank. Simply put, the internal structure of SDRAM is a storage array. Because it is a pipe-type storage (such as queuing to buy tickets), it is difficult to achieve random access.
The array is like a table. You can fill in the data as a table. Like table search, you can specify a row and a column to find the expected cells accurately, this is the basic principle of memory chip addressing. For memory, this cell can be called a storage unit. What is the name of this table (storage array? It is a logical Bank (L-bank ).

L-bank storage array

Because of technology, cost, and other reasons, it is impossible to make only one full-capacity L-bank, and most importantly, due to the limitation of the working principle of SDRAM, A single L-bank will cause very serious addressing conflicts and significantly reduce memory efficiency (this will be detailed later ). Therefore, we split the data into multiple L-banks in the SDRAM, which were two in the past and are basically four at present. This is also the maximum number of L-banks in the SDRAM specification. Up to 32 RDRAM instances are supported. In the latest DDR-ⅱ standard, the number of L-banks is increased to 8.
In this way, you must first determine the L-bank, and then select the corresponding row and column in the selected L-bank for addressing. It can be seen that the access to the memory can only be one L-bank at a time, and the data exchanged with the North Bridge each time is the capacity of a "storage unit" in the L-bank storage array. In some manufacturers' statements, the storage unit in L-bank is called word (here represents the set of bits rather than the set of bytes ).
As we can see from the past, the data size of the memory chip in one transmission rate is the chip Bit Width, so the capacity of this storage unit is the chip Bit Width (also the L-bank bit width, this relationship is only valid for SDRAM. The reason is described below.

2. memory chip capacity
Now we should be clear about the basic organizational structure of the memory chip. How is the memory capacity calculated? Obviously, the memory chip capacity is the total capacity of all l-banks. The method for calculating the number of storage units is the same as that for calculating the number of units in a table:
Number of storage units = number of rows × Number of columns (to obtain the number of storage units for an L-bank) × Number of L-Banks
In many memory product introduction documents, the capacity of the chip (or the chip specifications/organizational structure) is expressed in the m × w mode ). M is the total number of storage units in the chip. The unit is MB (M in short, with an exact value of 1048576 instead of 1000000). W represents the capacity of each storage unit, that is, the bit width of the SDRAM chip. The unit is bit. The calculated chip capacity is also measured in bytes. However, you can convert the size by dividing by 8 to byte ). For example, 8 m × 8 is an 8-bit wide chip with 8 m storage units with a total capacity of 64 Mbit (8 Mb ).

However, m × W is the simplest representation method. It is a company's representation of its memory chip capacity, which can be said to be one of the most formal forms.

Industry-standard memory chip capacity Representation

After calculation, we can find that the capacity of these three specifications is 128 Mbits, but the change in BIT width leads to a change in the number of storage units. From this example, we can also see that in the same total capacity, the bit width can adopt a variety of different designs.
3. dimm design related to chip Bit Width
Why is there a variety of designs for the Bit Width under the same total capacity? This is mainly to meet the needs of different fields. Now we know that the Bit Width of p-bank is fixed. That is to say, when the bit width is determined, the number of chips in a p-bank is naturally determined, as mentioned above, p-bank has requirements on the bit width of the chip set and has no restrictions on the capacity of the chip set. High-bit-width chips make the design of dimm simpler (because few chips are used). However, when the chip capacity is the same, the capacity of such dimm will certainly be inferior to that of modules using low-bit-width chips, because the latter can accommodate more chips in a p-bank. For example, in the above memory chip capacity identification diagram, the capacity is 128 Mbit, which is 16 Mb. If dimm is designed with a dual-p-bank + 16-bit chip, it can only accommodate 8 Chips, 128 MB. However, if a 4-Bit Width chip is used, the chip can accommodate 32 chips, which is 512 MB. The size of the dimm varies by 4 times, which indicates the importance of the chip width on the design of the dimm. Therefore, the 8-bit wide chip is a good choice between the capacity and cost balance on the desktop, so it is also the most popular in the market, and the chip higher than the 16-Bit Width is generally used in the case of larger width, for example, for graphics cards, the 4-Bit Width chip is obviously very suitable for large-capacity memory applications, basically not in the standard unbuffered module design.