Logical principle of X86 architecture CPU

This article is only a brief introduction to X86 's logical operation principle, does not involve the physical level and the assembly level knowledge.

First, the Vonloyman system operation process:

1, the history of the CPU is not torn, interested friends can search the Internet.

2, X86CPU is based on the Vonloyman architecture system, so basically nothing but these points:

①, instruction sets, and data are both represented in binary and are mixed into one memory.

②, computer is composed of arithmetic , controller , memory (cache), input device and output device . Ps:cache are different from registers, which are distributed among controllers and operators.

③, instructions are executed in a sequential order.

As shown in the following:

Second, the following are discussed in several major components:

Register: At the top level of the CPU storage pyramid, with the smallest capacity and the fastest (1-10 instruction cycles). The main function is to store the data for the operation of the computing device . Each has its own different functions.

Controller: Data register, instruction register, program counter, instruction decoder, timing generator, Operation Controller.

An operator: an operator consists of an arithmetic logic unit (ALU), an accumulator register, a data buffer register, and a status condition register.

Third, the implementation process:

When executing an instruction, the program counter first records the current address, puts him in the address Recorder , the program counter plus one (referring to the address of the next instruction),

The memory read instruction is then placed into the instruction register (IR). And then upload to the instruction decoder , the specific functions are as follows:

Instruction Decoder:

(1) Decoding analysis. Determine the operation that the instruction should complete, and generate a control potential for the corresponding operation. To participate in all the control commands (micro-operation control signals) required to form the function of the directive.

(2) According to the addressing method (8086 is to use the segment address + offset address synthesis of a 20bit addressing range, starting from 32bit to eliminate) the analysis and instruction function requirements, to form an effective address of the operand, and at this address to take out the operand (operational instructions) or to form a transfer address (transfer class instructions), To implement the program transfer.

The output of the opcode field in the instruction register is the input of the instruction decoder. Once the operation code is decoded, a specific signal can be sent to the operation controller for specific operation.

Timing Generator : A timing signal generator is a component that generates an instruction cycle control timing signal, and when the CPU begins to fetch instructions and executes instructions, the operation Controller takes advantage of the sequence of timing pulses generated by the timing signal generator and the different pulse intervals, It provides various micro-operation timing control signals required by each part of the computer, and directs the various parts of the machine in a orderly and rhythmic manner according to the specified time. (a method of distinguishing between data and instructions.) See the difference between my CPU architecture in detail)

Then pass the instruction to the operator. The register gets the decoded result, and the data is fetched from the data cache. The logical operations (and/or not) arithmetic operations are then performed according to the requirements and then transferred to the outside world via the data buffer registers to the IO port.

Operation Controller : The common control methods are synchronous control , asynchronous control and joint control .

1. Synchronous control mode: the operation of any instruction or the execution of each micro-operation in the instruction is controlled by a predetermined timing signal with a unified reference time scale. That is, all operations are controlled by a unified clock and are completed within standard time. (Under synchronous control, the end of each timing signal means that the scheduled work has been completed, and then the subsequent micro-operation is performed or automatically turned to the next instruction.) ）

2. Asynchronous control mode: There is no unified synchronization signal, the use of question and answer mode for timing coordination, the answer to the previous operation as the starting signal of the next operation.

3. Joint control: Combine synchronous control with asynchronous control. It is usually designed to use synchronous or synchronous control in the functional parts, and asynchronous mode among the functional parts.

And the arithmetic is roughly divided into logical operation (and or not) and numerical operation (in the form of addition into subtraction).

As shown in the following:

Attach a small animation: http://218.5.241.24:8018/C35/Course/ZCYL-HB/WLKJ/jy/Chap05/flash-htm/5.6.swf

Logical principle of X86 architecture CPU