A phase-locked loop and CPU clock. CPU Clock = phase-locked loop 0 output/CPU The Prescaler value of the clock configuration register is: fcpu=fcco/cclkcfg+1. The PLL can multiply the external clock to a higher frequency, and the PLL0 output frequency is:Fcco = (2xMxFin)/n;m=msel0+1,n=nsel0+1. MSEL0 and NSEL0 are the low and high characters of Pll0cfg_val respectively. n the value range is 1~32, and the value of M is at a higher oscillator frequency (more than 1MHz) the allowable range is 6~512. after the PLL0 output value is obtained, the CPU clock can be obtained after the CPU clock configuration register. In this system_lpc17xx.c file, you can modify the macro definition value for the # define Pll0cfg_val 0x00050063. For example: 00050063 This state PLL0 output 400MHz.M = 0x63 (16-binary) + 1 = 100 (10-binary);N = 0x05 + 1 = 6;Fcco = 2X12X100/6 = 400Mfcpu=fcco/2^ (cclkcfg+1) =400m/4=100m. The crossover value Cclksel can only be 0 and odd values (1, 3, 5...,255), cclk from the PLL0 output signal, by cclksel+ 1-Way Two: Timer clock: Timer can use PC and PR to re-divide Prescaler factor: LPC_TIM1->PR Timer count frequency =fcclk/lpc_tim1->pr Reload value: Lpc_tim0->mr0 time required to interrupt once = The count frequency of the overloaded value/timer. Http://blog.csdn.net/aquakguo0he1/article/details/8513923void delayms (uint8_t timer_num, uint32_t delayinms)
{
if (Timer_num = = 0)
{
LPC_TIM0->TCR = 0x02; /* Reset Timer */
LPC_TIM0->PR = 0x00; /* Set Prescaler to zero */
Lpc_tim0->mr0 = Delayinms * (9000000/1000-1);
Lpc_tim0->ir = 0xFF; /* Reset All Interrrupts */
LPC_TIM0->MCR = 0x04; /* Stop timer on Match */
LPC_TIM0->TCR = 0x01; /* Start Timer */
/* Wait until delay time has elapsed */
while (LPC_TIM0->TCR & 0x01);
}
else if (Timer_num = = 1)
{
LPC_TIM1->TCR = 0x02; /* Reset Timer */
LPC_TIM1->PR = 0x00; /* Set Prescaler to zero */
Lpc_tim1->mr0 = Delayinms * (9000000/1000-1);
Lpc_tim1->ir = 0xFF; /* Reset All Interrrupts */
LPC_TIM1->MCR = 0x04; /* Stop timer on Match */
LPC_TIM1->TCR = 0x01; /* Start Timer */
/* Wait until delay time has elapsed */
while (LPC_TIM1->TCR & 0x01);
}
Return
} Two systick:2.1 clock Source: CPU provides P3.26 (STCLK) 2.2 10ms dedicated interrupt. If you want to cycle interrupt, you have to load the streload regularly, the default time interval in the Stcalib 2.3 Bare Metal Timer
LPC1768 's Clock
