#define XTAL_FREQ 12000000
#define Vect_tab_offset 0x0000
void Systeminit(void)
{
PLL0 Clock Configuration
LPC_SC-SCS = 0X00000020; /* Enable external primary oscillator, frequency range 1-20m*/
if (lpc_sc, SCS & (1 << 5) /*/main clock enabled */
{
while (lpc_sc,SCS & (1<<6)) = = 0); /* Wait for the main crystal to enable and stabilize */
}
LPC_SC-cclkcfg = 0x00000003; /* Select the PLL to CCLK divide 4 */
LPC_SC-PCLKSEL0 = 0x00000000; /* Select peripheral clock from the CCLK of the split screen is 0, are 4-point frequency, later can be changed */
LPC_SC-PCLKSEL1 = 0x00000000;
LPC_SC-Clksrcsel = 0x00000001; /* Select the CCLK clock source main oscillator as the PLL0 clock source */
LPC_SC-pll0cfg = 0x00050063; /* Select PLL octave N 6 M pllout 400M */
LPC_SC-pll0feed = 0xAA;
LPC_SC-pll0feed = 0x55;
LPC_SC-Pll0con = 0x01; /* Enable PLL0 */
LPC_SC-pll0feed = 0xAA;
LPC_SC-pll0feed = 0x55;
while (!( LPC_SC, Pll0stat & (1<<)); /* Wait for PLL0 lock */
LPC_SC-Pll0con = 0x03; /* Enable PLL0 to connect and enable */
LPC_SC-pll0feed = 0xAA;
LPC_SC-pll0feed = 0x55;
while (!( LPC_SC, Pll0stat & (1<<) | (1<<))); /* Wait for the connection to succeed */
PLL1 Clock Configuration
LPC_SC-pll1cfg = 0x00000023; /* Set PLL1 divider M 3 P 2 */
LPC_SC-pll1feed = 0xAA;
LPC_SC-pll1feed = 0x55;
LPC_SC-Pll1con = 0x01; /* PLL1 Enable */
LPC_SC-pll1feed = 0xAA;
LPC_SC-pll1feed = 0x55;
while (!( LPC_SC, Pll1stat & (1<<)); /* Wait for PLL clock lock */
LPC_SC-Pll1con = 0x03; /* Enable and connect */
LPC_SC-pll1feed = 0xAA;
LPC_SC-pll1feed = 0x55;
while (!( LPC_SC, Pll1stat & (1<< 9) | (1<< 8) )); /* Wait for the connection to succeed */
LPC_SC-Pconp = 0x00000008; /* Initialize just open UART0 clock */
LPC_SC-clkoutcfg = 0x00000000; /* Do not use clock output */
LPC_SC-flashcfg = 0x0000403a; Set Flash access time
#if (__ram_mode__==1)//Based on configuration
SCB-Vtor = 0x10000000 | Vect_tab_offset;
#else
SCB-Vtor = 0x00000000 | Vect_tab_offset; Interrupt vector table in flash interval, offset to 0
#endif
}
lpc1768 system Clock