Lpc3250 perpheral Io Mapping

Machine description in board-smartarm3250.c: machine_start (lpc3xxx, "smartarm3250 board with the lpc3250 microcontroller")/* maintainer: Kevin wells, NXP Semiconductors */. phys_io = uart5_base ,. io_pg_offst = (io_p2v (uart5_base)> 18) & 0 xfffc ,. boot_params = 0x80000100 ,. map_io = maid, // CPU Io ing entry. init_irq = maid ,. timer = & lpc32xx_timer ,. init_machine = smartarm3250_board_init, Machine_end Io ing implements the lpc3250 porting code to map the on-chip I/O space with peripherals, including peripherals on the Iram, AHB Bus, FAB, and APB bus. Implement static struct map_desc lpc32xx_io_desc [] _ initdata = {// ahb0 bus space Io ing in the arch-lpc32xx.c. virtual = io_p2v (ahb0_start ),. PFN = _ phys_to_pfn (ahb0_start ),. length = ahb0_size ,. type = mt_device}, {// ahb1 bus space Io ing. virtual = io_p2v (ahb1_start ),. PFN = _ phys_to_pfn (ahb1_start ),. length = ahb1_size ,. type = mt_device}, {// FAB and APB bus space Io ing. virtual = io_p2v (fabapb_start ),. PFN = _ phys_to_pfn (fabapb_start ),. le Ngth = fabapb_size ,. type = mt_device}, {// Iram space Io ing. virtual = io_p2v (iram_base ),. PFN = _ phys_to_pfn (iram_base ),. length = (sz_64k * 4 ),. type = mt_device },}; void _ init lpc32xx_map_io (void) {iotable_init (lpc32xx_io_desc, array_size (lpc32xx_io_desc);} the macro definition involved is in platform. the macro definition used in the H file. Take ahb0 as an example: /** AHB 0 physical base addresses */# define slc_base 0x20020000 # define ssp0_base 0x20084000 # define spi1_base 0x20088000 # define ssp1_base 0x2008c000 # define spi2_base 0x20090000 # define i2s0_base 0x20094000 # define sd_base 0x20098000 # define i2s1_base 0x2009c000 # define mlc_base 0x200a8000 # define ahb0_start slc_base # define ahb0_size (mlc_base-slc_base) + sz_4k) extended reading specific Io ing for adding users. If you want to expand the device, you need to add When I/O ing is added, you can modify. map_io as the User-Defined io_map function, and call the io_map function of the CPU in the Custom io_map function. The following is a mainstone System Based on PXA270. First declare a map_desc structure, and then call the iotable_init function in the Custom io_map function to initialize the user space ing: 610 static struct map_desc mainstone_io_desc [] _ initdata = {611 {/* CPLD */612. virtual = mst_fpga_virt, 613. PFN = _ phys_to_pfn (mst_fpga_phys), 614. length = 0x00100000,615. type = mt_device616} 617}; 618619 static void _ init mainstone_map_io (void) 620 {621 pxa_map_io (); 622 iotable_init (mainstone_io_desc, array_size (mainstone_io_desc) ); 623624/* for use I SRAM as framebuffer. */625 pslr | = 0xf04; 626 pcfr = 0x66; 627} 628629 machine_start (mainstone, "Intel hcddbbva0 Development Platform (aka mainstone)") 630/* maintainer: montavista Software Inc. */631. phys_ I/o = 0x40000000,632. boot_params = 0xa0000100,/* blob boot parameter setting */633. io_pg_offst = (io_p2v (0x40000000)> 18) & 0 xfffc, 634. map_io = mainstone_map_io, // Io Space Map 635. init_irq = mainstone_init_irq, 636. timer = & pxa_timer, 637. init_machine = mainstone_init, 638 machine_end _ phys_to_pfn in arch/ARM/include/ASM/memory. definition in the hfile: 120/* 121 * convert a physical address to a page frame number and back122 */123 # DEFINE _ phys_to_pfn (paddr)> page_shift) 124 # DEFINE _ pfn_to_phys (PFn) <page_shift) and the following is the io_p2v implementation of the lpc3250:/* Start of virtual Addresses for Io devices */# define io_base 0xf0000000 # define io_p2v (x) (io_base | (x) & 0xff000000)> 4) | (x) & 0x000fffff )) # define io_v2p (x) & 0x0ff00000) <4) | (x) & 0x000fffff) page_shift see ARCH/ARM/include/ASM/page. hfile: 13/* page_shift determines the page size */14 # define page_shift 12 15 # define page_size (1ul <page_shift) 16 # define page_mask (~ (PAGE_SIZE-1) io_p2v each processor has its own io_p2v implementation, the following is the PXA270 processor, see ARCH/ARM/Mach-PXA/include/Mach/hardware. h file: 28/* 29 * Intel pxa2xx internal register mapping: 30*31*0x40000000-0x41ffffff <--> 0xf2000000-0xf3ffffff 32*0x44000000-0x45ffffff <--> 0xf4000000-000033*0x48000000-0x49ffffff <--> 0xf6000000-00- 000034*0x4c000000-0000< --> 0xf8000000-000035*0x50000000-0x51ffffff <--> 0xfa000000-0 xfbffffff 36*0x54000000-0x55ffffff <--> 0xfc000000-0 xfdffff 37*0x58000000-0x59ffffff <--> 0xfe000000-0 xffffffff 38*39 * Note that not all pxa2xx chips implement all those addresses, and the 40 * kernel only maps the minimum needed range of this mapping. 41 */42 # define io_p2v (x) (0xf2000000 + (x) & 0x01ffffff) + (x) & 0x1c000000)> 1 )) 43 # define io_v2p (x) (0x3c000000 + (x) & 0x01ffffff) + (x) & 0x0e000000) <1 )) add extended device register 18 # define 1_pxa_cs2_phys 19 # define mst_fpga_virt (0xf0000000) 20 # define mst_p2v (x)-Limit + limit) 21 # define mst_v2p (X) (x)-mst_fpga_virt + mst_fpga_phys) 22 23 # ifndef _ Assembly _ 24 # DEFINE _ mst_reg (x) (* (volatile unsigned long *) mst_p2v (x) 25 # else 26 # DEFINE _ mst_reg (x) mst_p2v (X) 27 # endif 28 29/* board level registers in the FPGA */30 31 # define mst_leddat1 _ mst_reg (0x08000010) 32 # define mst_leddat2 _ mst_reg (0x08000014) 33 # define mst_ledctrl _ mst_reg (0x08000040) 34 # define mst_gpswr _ mst_reg (0x08000060) 35 # define mst_mscwr1 _ mst_reg (0x08000080) 36 # define mst_mscwr2 _ mst_reg (0x08000084) 37 # define mst_mscwr3 _ mst_reg (0x08000088) 38 # define mst_mscrd _ mst_reg (0x08000090) 39 # define primary _ mst_reg (0x081_c0) 40 # define primary _ mst_reg (0x081_d0) 41 # define primary _ mst_reg (0x081_e0) 42 # define primary _ mst_reg (0x081_e4)