LPC4370 acdhs Speed and DMA

LPC4370 acdhs Speed

AHB clock base_m4_clk clk_m4_adchs up to 204 MHz. For register interface.

Adchs clock base_adchs_clk clk_adchs up to 80MHz for conversion.

How does I set up the BASE_M4_CLK or the AHB clocks for a high speed ADC?

How does I verify the BASE_ADCHS_CLK is running (204Mhz) fast enough for 80Msample?

But in reality, the HSADC clock structure are very simple and can be setup by directly setting the HSADC base clock with th is one function:

baseclock_xxxx true false);

You can attach the HSADC base clock to any of the following clock inputs:

/** * @brief CGU Clock Input list * These is possible input clocks for the CGU and can come * from both external (cryst AL) and internal (PLL) sources. These * clock inputs can be routed to the base clocks (@ref chip_cgu_base_clk_t). */typedefenumChip_cgu_clkin {clkin_32k,/*!< External 32KHz input*/Clkin_irc,/*!< Internal IRC (12MHz) input*/Clkin_enet_rx,/*!< External enet_rx pin input*/Clkin_enet_tx,/*!< External enet_tx pin input*/ Clkin_clkin,  /*!< External gpclkin pin input  *  /clkin_reserved1, Clkin_crystal,/*!< External (main) crystal pin input*/CLKIN_USBPLL,/*!< Internal USB PLL input*/CLKIN_AUDIOPLL,/*!< Internal Audio PLL input*/ CLKIN_MAINPLL,  /*!< Internal Main PLL input  *  /Clkin_reserved2, Clkin_reserved3, Clkin_idiva,/*!< Internal divider A Input*/CLKIN_IDIVB,/*!< Internal divider B Input*/CLKIN_IDIVC,/*!< Internal divider C Input*/CLKIN_IDIVD,/*!< Internal divider D Input*/clkin_idive,/*!< Internal divider E Input*/CLKINPUT_PD/*!< External 32KHz input*/} chip_cgu_clkin_t;

Connect the 204MHz main PLL to a divider input, set the divider to 3, and use the divider for the HSADC base clock.

Gives 204/3 = 68Mhz. Just make sure-aren ' t using those dividers for anything else!

CLKIN_MAINPLL 3 /*  */Clkin_idivatruefalse/* */

use the USB PLL rate (typically 480MHz) with a divide by 6 to get 80MHz. (Note Different dividers have different maximum divider values)

/**/clkin_usbpll6/**/CLKIN_IDIVD  truefalse/* */

I think you might isn't being getting MHz you'll be getting 2MHz, as the only divider so can be sourced from USB0PLL are Divider A

(Max divider value supported by Div_a are 4), if you attempt to source others [Div_b to Div_d] from USB0PLL it Would default to IRC (12MHz).

Hence you'll get "IRC CLK"/6 as the output. To get an MHz you can try the following

Chip_usb0_init ();/*Initialize the USB0 PLL to 480 MHz*/Chip_clock_setdivider (clk_idiv_a, CLKIN_USBPLL,2);/*Source div_a from USB0PLL, and set divider to 2 (Max DIV value supported is 4) [in 480 MHz; Out MHz*/Chip_clock_setdivider (Clk_idiv_b, Clkin_idiva,3);/*Source Div_b from Div_a, [in MHz; out-of-MHz*/Chip_clock_setbaseclock (Clk_base_adchs, CLKIN_IDIVB,true,false);/*Source Adhcs Base clock from Div_b*/chip_clock_enableopts (Clk_adchs,true,true,1);/*Enable the Clock*/

480MHZ/2/3 = MHz 

Finally I ' ve got some adequate results. Adchs clock is 80MHz, but the sample rate was only 40Msps and not 80Msps as I expected.

Chip_clock_enableopts (clk_adchstruetrue1/** /

Every time I ' ve tried to set samplerate to values more than 4000000-uart stopped working.

Is it real to get 80Msps?

The original hsadc.c file used TIMER1 to trigger a software event to trigger to start the ADC.

In my modification I tried to us the TIMMER1 to stop the ADC sampling but it does not work.

I found that there were too many IRQ events (with higher priority than the UART) causing the UART not to get service /c8>

And also the descriptor would not update.

I left the code in and set the "samplerate to" which cause TIMER1 to file every 10ms.

I used this to toggle GPIO Port 3 bit 7 for testing.

1111111111111

LPC4370 acdhs Speed and DMA