LUTs, Flip-flop, Slice

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_basic_chip_terms/reprinted flip-flops, LUTs, and Slices

Logic resources is grouped in slices to create configurable logic blocks.

A slice contains a set number of LUTs, flip-flops and multiplexers. (with multiplexers?)

A LUT is a collection of logic gates hard-wired on the FPGA. LUTs Store a predefined list of outputs for every combination of inputs and provide a fast-to-Retrieve the OU Tput of a logic operation.

A flip-flop is a circuit capable of the stable states and represents a single bit.

A multiplexer, also known as a MUX, is a circuit that selects between to or more inputs and outputs the selected input.

Different FPGA families implement slices and LUTs differently. For example, the a slice on a virtex-ii FPGAs has both LUTs and a flip-flops but a slice on a Virtex-5 FPGAs have four LUTs and Four flip-flops. In addition, the number of inputs to a LUT, commonly and six, depend on the FPGA family.

Registers

A register is a group of flip-flops that stores a bit pattern. A register on the FPGA has a clock, input data, output data, and enable signal port. Every clock cycle, the input data is latched, stored internally, and the output data are updated to match the internally St ORed data. FPGA VIs Use registers to perform the following functions:

• Holding state between iterations of a loop
• I/O synchronization
• handshaking data between clock domains
• Pipelining
• Communicating with a host VI

The logical resources of FPGA are composed of slice elements. Each slice contains a lut and a flip-flop. LUTs is the lookup table, which outputs the result according to the input combination; Flip-flop is the status register. Remember: A single Reg uses flip-flop resources, and if Reg writes RAM, it uses Luts or Bram resources

LUTs, Flip-flop, Slice