[]makefile Document writing rules and examples

Http://xueqi.iteye.com/blog/1567866 1. A simple Makefile example   assume that a program has two files file1.c,file2.c, each file contains Head.h, Generate File Executable  file:file1.o file2.o                   Affiliated rows (file dependencies)     Gcc-o file1.o file2.o             command line file1.o:file1.c head.h    gcc-c file1.cfile2.o:file2.c head.h    gcc-c file2.c  starts backward from the file final target, lists the dependencies of the file, and make at Execution:  (1) determines if the file executable exists, if it does not exist, Executes the command line, looking down on the dependency (2) if file exists, then check the dependent files, whether there is an update, if there is an update to execute the command line, if there is no update to give the hint:    make: ' file ' was up to date.  Macro definitions and internal variables   macro definitions in 2.makefile: OBJS = file1.o FILE2.OCC = gcccflags =-wall-o-g  reference: file:$ (OBJS)     $ (CC) $ (OBJS)-o filefile1.o:file1.c head.h    $ (cc) $ (FLAGS)  -c file1.c  file2.o : file2.c head.h    $ (CC) $ (FLAGS)  -c file2.c  internal variable:  [email protEcted]: The destination file name of the current rule $<: Depends on the first of the list depends on the file $^: Entire dependency list  file:$ (OBJS)     $ (CC) $^-O [email  protected]file1.o:file1.c head.h    $ (CC) $ (FLAGS)-C $<-O [email protected]file2.o:file2.c head.h    $ (CC) $ (flags)-C $<-o [email protected]  "$ (CC) $ (flags)-C $<-O [email p Rotected] "is an implied rule that can be used without writing, and the default is to use this rule  3. Illusion   Assume a project to generate two executables file1 and File2, the two files are phase independent, at the beginning of makefile:  all: File1 File2 make always assumes that all is to be generated, to check its dependent file  4. Clear files generated by make  clean:    RM *.o     RM file  Execute: Make clean clears the *.O and file files generated by makes if a clean file exists, then the purge will not be performed (because the cleaner has no dependent files, always up-to-date)   uses the phony target , to avoid conflicting files with the same name, do not check the clean file exists or not, to perform a purge operation   phony : Cleanclean:

RM *.O

The RM file 5.makefile function searches the current directory, generates a list of files terminated by *.C, wildcard--function name SOURCE = $ (wildcard *.c) with%.O to replace the%.c file in $ (SOURCE) Objs = $ (patsubst %.c,%. o,$ (SOURCE)) 6. Generate new Rule SOURCE = $ (wildcard *.c) depends:$ (source) Gcc-m $ (source) > depends (Generate rules for each. c file, c files and related header files are dependent on In the makefile file: include depends 7. A valid makefile file can do most of the dependency checks we need, without making too many changes to function in most projects: Search the current directory, find the source file, put it into the source variable, Use PATSUBST to generate the target file (*.o) CC = Gcccflags =-wall-o-G SOURCE = $ (wildcard *.c,*.cc) Objs = $ (Patsubst%.c,%.o,$ (patsubst,%.cc, %.o,$ (SOURCE)) file:$ (OBJS) $ (CC) $^-o [email protected] Generate target file with default rules (*.O)

1: Compile the executable program. 2: Compiling Lib Library 3: compiling so Library
This blog for the above three kinds of purpose of each write makefile template, hope to help you.
I. Compiling an executable program
Compile files in the current directory into executables (you can only Change Inc and LIB if you connect to an external library)

CXX = g++
TARGET = Bitmaploctest
C_flags + =-G-wall
Lib_flags =-Pthread
All: $ (TARGET)
BITMAPLOCTEST:BITMAPLOCTEST.O BITMAPLOC.O FILE_LOCK.O
$ (CXX)-o [email protected] $^ $ (lib_flags) $ (LIB) $ (c_flags)
. CPP.O:
$ (CXX)-C-o $*. O $ (INC) $ (c_flags) $*. cpp
. CC.O:
$ (CXX)-C-o $*. O $ (INC) $ (c_flags) $*. cc
Clean
-Rm-f *. o $ (TARGET)

Two. Compiling into Lib Library
The specified files in the current directory are compiled into Lib libraries (generally LIB libraries will not compile the external libraries used when compiling, but rather when compiled into executable programs or. So)

Inc_dir=./
Src_dir=./
Obj_dir=./
Lib_dir=./
H_dir=./
obj_ext=. O
cxxsrc_ext=. cpp
Csrc_ext=. C
Lib_ext=. A
h_ext=. h
OBJECTS = $ (obj_dir) bitmaploc$ (obj_ext) \
$ (Obj_dir) file_lock$ (Obj_ext)
Lib_target = $ (lib_dir) libbitmaploc$ (Lib_ext)
$ (obj_dir)% $ (obj_ext): $ (src_dir)% $ (cxxsrc_ext)
@echo
@echo "compiling $< = = > [email protected] ..."
$ (CXX) $ (INC) $ (c_flags)-C $<-o [email protected]
$ (obj_dir)% $ (obj_ext): $ (src_dir)% $ (csrc_ext)
@echo
@echo "compiling $< = = > [email protected] ..."
$ (CC)-i./$ (INC) $ (c_flags)-C $<-o [email protected]
All: $ (lib_target)
$ (Lib_target): $ (OBJECTS)
All: $ (OBJECTS)
@echo
$ (AR) RC $ (lib_target) $ (OBJECTS)
@echo "OK"
Clean
Rm-f $ (lib_target) $ (OBJECTS)

Three. Compiling into so library
The specified files in the current directory are compiled into so libraries (all referenced external libraries must be compiled)

CC = gcc
CXX = g++
CFLAGS =-Wall-pipe-ddebug-d_new_lic-g-d_gnu_source-shared-d_reentrant
LIB =-Lconfig-ldl-lrt-l. / .. /lib-lttc-g
INCLUDE =-I.. /Spp_inc
OO = service.o tinystr.o tinyxml.o tinyxmlerror.o tinyxmlparser.o uin_conf.o STAT.O
TARGETS =.. / .. /lib/libranch.so
All: $ (TARGETS)
Stat:tool_stat.cpp
$ (CXX) $ (INCLUDE) tool_stat.cpp-o tool_stat stat.o tinystr.o tinyxml.o tinyxmlerror.o tinyxmlparser.o-g
CP Tool_stat. / .. /bin
$ (TARGETS): $ (OO)
$ (CXX) $ (CFLAGS) $ (INCLUDE) $ (OO)-o [email protected] $ (libdir) $ (LIB)
. C.O:
$ (CC) $ (CFLAGS)-C $ (INCLUDE) $<
echo [email protected]
. CPP.O:
$ (CXX) $ (CFLAGS)-C $ (INCLUDE) $<
echo [email protected]
%:%. C
$ (CC) $ (CFLAGS)-o [email protected] $< $ (OO) $ (ldflags)
echo [email protected]
Clean
Rm-f *. o
Rm-f $ (TARGETS)
Rm-f Tool_stat

Cc=cc-g Proc=proc cflags=-dprecomp-i$ (oracle_home)/precomp/public \ -i$ (Oracle_home)/xdk/include-i. Flags=-d_all_source=1-d_linux-g-I.. /.. /incl-d_gnu_source-d_is_eab=1-d__use_gnu=1-d__gcc_296-i/usr/include/libxml2-i. /csrc-i. /.. /csrc/-dposix=1-dlinux libhome=$ (Oracle_home)/lib Llibsql= ' cat $ (libhome)/sysliblist ' \ ' Cat $ (libhome)/ldflags ' \ -lclntsh libs=-l$ (libhome) $ (llibsql)-lmylib . Suffixes:. sqc. C. o %.c:%.sqc $ (PROC) $ (procplsflags) iname=$^ Hold_cursor=yes %.o:%.c $ (CC)-C $ (FLAGS) $ (LIBS) $^ TEST:TEST.O TEST1.O TEST1.O Cc-o [email protected] $ (FLAGS) $ (LIBS) $^ RM-RF $^ HAHA:TEST.O TEST1.O TEST1.O @echo "+ =" $+ @echo "? =" $? @echo "^=" $^ @echo "<=" $< @echo "@=" [email protected] @echo "*=" $* @echo "%=" $%

2. Description

2. 1 General Makefile writing has 3 steps

1. Macro definition. The main function is to define some macro variables that have replaced the longer compilation support information. In general, the library file path for. h header files,. a/.so are required for compilation. For example, Cflags is the header file path that Oracle precompilation requires for database support. Libhome is the database library file path required for Oracle Environment compilation.

2. The interdependence between source files. Lists the files that need to generate the target file compilation dependency. For example, the test target, when produced will detect (TEST.O TEST1.O test1.o) These dependent file changes, if the dependent file changes will automatically compile the dependent file.

3. The executable command. That is, the compilation behavior that is made against the target relationship. For example, test is executed after detecting the dependent file (cc-o [email protected] $ (CFLAGS) $ (LIBS) $^) Compile the link to produce the target execution file test.

4. Macro use (), {} to confirm that the macro name such as ${lib} plus {} will find the macro content of LIB, $LIB will find the macro content of L.

2.2: Common compilation Item description

1. -I: Make the path to the header file search

2. -L: Connect the required library file path

3.–l: Connect the required library files (e.g.: libmylib.so writing –lmylib)

2.3: Automation Variable Description:

$+: All dependent files, separated by spaces, and in order of occurrence, may contain duplicate dependent files.

$?: all dependent files separated by spaces, these dependent files are modified later than the target's creation date

$^: All dependent files, separated by spaces, do not contain duplicate dependent files.
$<: The name of the first dependent file.
[Email protected]: The full name of the target.

$*: The name of the target file that does not contain the extension.
$%: If the target is an archive member, the variable represents the archive member name of the target.

In contrast with the above makefile, perform make haha to get the following control information:

$ makehaha

TEST.OTEST1.O TEST1.O

test.otest1.o

test.otest1.o

Test.o

haha

2.4: Suffix rule:

. Suffixes:.sqc. C. o Develop a new suffix rule. (%.C:%.SQC), (%.o:%.c) is the rule behavior. is to convert all. SQC to. C,.c and then to. O.

. C.O: Equivalent to%.O:%.C

3. Attention:

There is no further content behind the line break.

Hyphenation best to use ^i (Tab key)

Comment Symbol #

Include contains compiled files

1. Overview

Makefile,what?? Many Windows programs may not have heard of
To put it simply, Makefile is a document that describes the compilation, connection, and other rules of the entire project under the Unix/linux environment, which consists mainly of three points:
1) which source files in the project need to be compiled and how to compile
2) Dependent library and location of library
3) What do you want: executable file? Static library? Dynamic library?
Project, we will have a lot of source files, header files, dependent library files, configuration files and so on, through the makefile definition rules to develop the compilation sequence, compile rules, compile dependencies, and even more complex functions, will greatly facilitate our development, its greatest advantage is "automated compilation", through the ' Make ' makes it easy to compile your entire project.

2. Compiling links

From the source code to the executable file, the specific steps:
SOURCE---> Preprocessing---> Compilation---> Assembly---> Links
We often refer to the three phases of preprocessing, compilation, and assembly as the compile phase, at which time the compiler checks the program syntax, the function and the variable declaration, and so on.
After compiling, Unix/linux will get an. o file (in general, each source file can generate a corresponding. o file), which is the object File (the. obj file under Windows),. O cannot be run directly, we need to synthesize the executable file, this process is called the link. During the linking process, the linker will look for the implementation of the function in all the. o files, and will report a link error if it is not found.

3.Makefile rules

Makefile has only one rule:

Target:prerequisites
Command

Target: The destination, which can be an executable file, can be an. o file, or it can be a label, simply put, it is what you do.
Prerequisites: The condition required to generate a target, which can be a file or another target
Command: Specific commands to execute

This is explained as follows: Target is dependent on the file in prerequisites and its generation rules are defined in the command.
A simpler expression: if the time of any of the files in the prerequisites is newer than the target file, command-defined commands are executed.

eg
=====makefile=====
#第一个规则
TEST:MAIN.O hello.o
GCC MAIN.O hello.o–o Test

#第二个规则
Main.o:main.c
Gcc–c MAIN.C

#第三个规则
HELLO.O:HELLO.C hello.h
Gcc–c hello.c

#第四个规则
Clean:
RM–RF *.O
RM–RF Test
=====makefile=====

First rule:
Test is target, MAIN.O and hello.o are prerequisites, ' gcc main.o hello.o–o test ' is command.
That is: to generate test, you need to have MAIN.O and hello.o, if the MAIN.O or hello.o file time than test new (or test file does not exist), will execute the command ' gcc main.o hello.o–o test ',

A second rule:
Target is main.o,main.c is prerequisites, ' gcc–c main.c ' is command
That is: to generate test, you need to MAIN.C, if the Main.c file time is newer than MAIN.O, will execute ' gcc–c main.c '

A third rule is similar to the second rule

Fourth rule:
Here, target is clean, here, clean is not a file, but an action name, its execution, needs to be shown in the Make command after making, for example, here to execute ' made clean ', will invoke the subsequent command, namely ' RM–RF *.O RM – RF test ', in addition, there is no prerequisites here, that is, execute command at any time

Let's look at what the ' make ' will do if it does:

1. Make will find the file named "Makefile" or "Makefile" in the current directory.
2, if found, it will find the file in the first target file (target), in the above example, he will find the "test" this file, and the file as the final target file.
3, if the test file does not exist, or test depends on the [. O] File modification time is newer than the test this file, then he will execute the command defined later to generate test this file.
4. If the. o file on which test depends is present, make will find the dependency of the. o file in the current file and, if found, then generate the. o file based on that rule.
5, and so on, until all of the generated target are up-to-date.

If the user executes ' make clean ' because there is no dependency behind it, execute the command-defined commands.

If we modify the code MAIN.C and then execute ' make ', because the main.c time is newer than MAIN.O, then MAIN.O will recompile the build, and the test will regenerate because the MAIN.O file is newer than test.

[]makefile Document writing rules and examples