Mathematical Principles of integer binary complement (two's complement)

I recently re-learned the CPU architecture, used the binary complement principle to eliminate the differences between the number of symbols and the number of unsigned numbers, and integrated the subtraction calculator to the addition calculator, therefore, I was very interested in simplifying the design of CPU hardware. So I thought about some articles about two's complement on the Internet, but most of them are too academic and sorted out, I want to express it in a concise way. For the sake of simplicity, I used a four-character long register as an example. 32-bit and 64-bit are the same. For more information about the mathematical principles of code complementing, see wikipedia's articles on one's complement and two's complement.

The hardware design is concise as the goal, so it is best to add only integer operations, and do not have to perform special processing on the symbol bit, can this goal be achieved? Of course you can, that is, use the two's complement. The so-called complement is actually for the signed number, which means that a positive number uses the original code, the negative number is expressed by the absolute value of the exponential negative number of the Word Length of 2, that is, x = pow (2, word_length)-abs (x ), the simple calculation method of this complement code is what we often say in the computation machine book. The absolute value of x is reversed by 1. Now you know the real calculation method of the complement code. Why do we need to express a negative number as this? This is a mathematical principle. This is exactly what needs to be explained in this article. After a full understanding of the general purpose instructions programming of common CPU commands, it lays a solid foundation (general purpose instructions are all for integers ), the floating point number calculation specification may be added later.

Now let's look at a subtraction:
7-6 (type 1)
Can it be converted into an addition? Let me try:
7 + (16-6)-16 (Type 2)
16 is the smallest overflow Number of 4-bit registers (2 ** 4 ** indicates the pow operation). The two substatements above are completely equivalent, in our opinion, the second sub-statement is the method used by the integer computing unit inside the CPU. For some special reasons, the CPU only needs to calculate the first addition, the remaining two subtraction methods are automatically truncated by the compiler, person, or register.
As described above, we know that 16-6 is the complement code of-6 on a 4-digit long machine. In this step, the computation is generally completed by the compiler and the negative number is directly stored as the complement code, this is 1010. Let's take a look at how the CPU is computed:
0 1 1 1 (7)
+ 1 0 1 0 (10)
---------------------
1 0 0 0 1 (17)

The above formula completes the first two steps in formula (2), and requires 16 minus to get the correct result. The magic is that the machine is 4 characters long, therefore, the fifth digit 1 is discarded directly, that is, overflow, which is equivalent to automatically reducing 16. Therefore, the final result is 0001, which is equal to 1. All the calculations in formula 2 are completed, now that you have obtained the correct result, you should understand why the minimum overflow number is used to complete the subtrahend In the complement conversion. This is to achieve automatic overflow and the final subtraction.

Let's take a look at the addition of two negative numbers to see how the CPU treats them as pure binary operations, but the results are not bad at all:
(-6) + (-7) (Type 3)
Replace it with the following formula based on the above rule:
[(16-6)-16] + [(16-7)-16] (formula 4)
The (16-6) and (16-7) Sections have been completed by the compiler, which is the complement code corresponding to the negative number. Let's take a look at the CPU computing content:
1 0 1 0 (10)
+ 1 0 0 1 (9)
-----------------
1 0 0 1 1 (19)

In formula 4, two more 16 s are required. Here, the 5th-bit overflow has been automatically reduced to 16 S. We need to subtract 16 s to get the correct result, but the result in the register is 0011, based on this result, I don't know whether this is the final value or whether it still needs to be reduced by 16, which is too bad. The cause is that if all four-bit registers are used to store the value, the binary ambiguity of the number of symbols is generated. For example,-9 is represented by a binary complement (16-9), and the binary value is 0111, which is the same as 7 of the integer, I can't know whether the binary string is-9 or 7. Well, I am really smart and have come up with a solution. Hey, let's take a look at the binary values that can be stored in four registers:
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
I can use the highest digit as a sign for interpreting the number symbol. If it is 0, I will be interpreted as a positive number. If it is 1, I will be interpreted as a negative number. If it is interpreted as a positive number, no more 16 is needed, the result is the final result directly. If it is a negative number, you still need to subtract 16 to get the final result, because we use 16-x to represent-x, just as a positive number and a negative number are half (assuming 0 is a positive number), return to the above problem and (-6) + (-7) the CPU register is eventually 0011. when I should be a positive number, positive numbers do not need to be reduced by 16, so the last value is 3. No! It should be-13. We still need to reduce the number by 16, but we just mentioned that positive numbers do not need to be reduced. What's wrong? Think about it.
It turns out that if we explain the binary data in the preceding way, the range of the Four Binary values can only be [-8 ~ 7], in fact, if the register overflows from the left side, its value is in [... 0 \ 1 \ 2 \ 3 \ 4 \ 5 \ 6 \ 7 \-8 \-7 \-6 \-5 \-4 \-3 \-2 \-1 \ 0...] this is a continuous loop. That is to say, the previous-13 is rounded from-8 to the left and returns to 3 again. We must have a way to determine the overflow, if we interpret the binary values in the register as the unsigned number, it is very simple. As long as the highest value is the generated carry, it will overflow. If we interpret the number as the signed number, how can we check whether the last value overflows?
This is the essence of the math principle. With this reasoning, the CPU can process the numbers of symbols and unsigned numbers equally. Let's analyze the math principle carefully, in the CPU's view, the registers are purely binary, which is equivalent to the number of unsigned values. If the two numbers are added, the highest bit generates a carry value, which indicates that the result must be in the range of [16 ~ 30]. If the secondary high position generates carry to the highest bit, it indicates that the result range of the Three-bit addition is [8 ~ 14] Because the highest bit overflow is discarded, it indicates that the final result is reduced by 16, and the next high to the highest bit produces carry, indicating that the final result is at least 8. Now there are several conclusions as follows:
(1) If the highest bit has a forward digit and the second highest bit has a forward digit, the final result is located in [-8 ~ 6]
(2) If the highest bit has an inner, and the second highest bit has no carry, the final result is in [-16 ~ -9]
(3) If the highest bit has no carry, and the second highest bit has a carry, the final result is located in [8 ~ 14]
(4) If the highest bit has no carry, and the secondary high has no carry, the final result is located in [0 ~ 7]
The signed interpretation method determines the range of numbers [-8 ~ 7]. How can we see at a glance how to determine whether the computing with the symbol number overflows!

Let's take a look at the six most commonly used flag bits in the cpu eflags register: CF, PF, AF, ZF, SF, OF. I only explain CF and, the remaining four are well understood. CF indicates that the highest bit of the two operands is carried in binary integer calculation. It is clearly used to determine whether the unsigned number overflows, and OF is the XOR value OF whether the register is carried to the highest position (carry 1, otherwise 0) and the CF bit. Is it amazing, the last four rules are described to determine whether a signed integer overflows.

Isn't it possible to imagine that there are so many principles behind the complement specifications used for integer computation in a general book? These features determine that the processor uses the binary complement code for integer computation during design, the addition and subtraction operations of the number of BITs and the number of unsigned bits are all implemented by the addition operation of the number of unsigned bits, greatly simplifying the circuit implementation, increasing the processor efficiency and reducing the design and manufacturing costs. However, the multiplication/Division operations of integers cannot be processed in this way. That is why there are signed multiplication/division commands, but there are no addition or subtraction commands. In a sense, in fact, the subtraction command is only a package of the addition command, because there is no subtraction logic inside the CPU, only addition.