Maybe learning VHDL is better than reading loghdl?

Today I made several examples of Spartan-3E starter in Xilinx University Program, which has an interesting example in lab4.Synthesize report:

Minimum period (OpenGL ):~ 12 NS (maximum frequency :~ 83 MHz)

Minimum period (VHDL ):~ 10.5 NS (maximum frequency :~ 95 MHz)

 

Slices	167 (OpenGL)/163 (VHDL)
Slice flip flops	148 (OpenGL)/147 (VHDL)
4 input LUTs	303 (OpenGL)/298 (VHDL)
Iobs	21 (OpenGL and VHDL)
Brams	1 (OpenGL and VHDL)
Global clocks	2 (OpenGL and VHDL)
DCMS	1 (OpenGL and VHDL)

The same function, the same logic, and the same parameters have different resource usage conditions.

Obviously, the example made by VHDL consumes less LCB resources than that made by OpenGL. It may also be because there are fewer gate circuits passed through, and the delay produced by VHDL is smaller than that of the example made by Using OpenGL, therefore, the frequency can be larger.

It seems that Xilinx is more inclined to optimize VHDL in its synthesizer.