MCU Interrupt System

The single-chip Interrupt System Concept: What is interrupt, we introduce it from a routine in life. When you were reading a book at home, the phone suddenly rang. You put down the book, answered the phone, talked to the caller, put down the phone, and came back to continue reading your book. This is the phenomenon of "interruption" in life, that is, the normal working process is interrupted by external events. The interruption in our daily life is also very beneficial for us to learn the interruption of single chip microcomputer.

First, what can be interrupted, and many events in life can cause interruptions: When someone rings the doorbell, the phone rings, and your alarm goes off, the water you burned is boiling .... And so on, we call it the interrupt source that can cause the interruption. There are also some events that can cause the interruption in the single chip microcomputer. There are five events in 8031: two external interruptions, two counts/Timers are interrupted, and one serial port is interrupted.

Second, nesting of interruptions and priority handling: imagine that we are reading a book, the phone rings, and another person presses the doorbell. What should you do first? If you are waiting for a very important phone call, you will not pay attention to the doorbell. Otherwise, you may not pay attention to the phone if you are waiting for an important guest. If they are not the two (that is, waiting for a call or waiting for a visit), you may deal with them according to your usual habits. In short, there is a problem of priority, which is also true for single-chip microcomputer. The priority issue occurs not only when two interruptions occur at the same time, but also when an interruption occurs, for example, you are answering the phone, when someone rings the doorbell, or you are opening a door to talk to someone, and the phone rings again. Consider what we will do.

Third, the response process of Interruption: when an event occurs, we must remember the page on which the current book is read or put a bookmark on the current page, then we will deal with different things (because we have finished processing, we will come back to continue reading): we will go to the place where the phone rings, and we will go to the door when the doorbell rings, that is to say, we have to deal with different interruptions in different locations, which are often fixed. This approach is also used in the computer. There are five interrupt sources. After each interrupt is generated, the program is located in a fixed place to process the interrupt, of course, before you proceed, you must first save the address of the command that will be executed below, so that after the interruption is handled, you can go back to the original place to continue executing the program. Specifically, the interrupt response can be divided into the following steps: 1. To protect the breakpoint, that is, to save the address of the next command to be executed, this address is sent to the stack. 2. Find the interrupt entry. Find 5 different endpoints Based on the interruptions caused by five different interrupt sources. The above work is automatically completed by the computer and has nothing to do with programmers. There are interrupt handlers in these five entry addresses (this is where the program was written. If the interrupt program was not put there, it would be wrong, the interrupted program cannot be executed ). 3. Execute the interrupt processing program. 4. Interrupt return: After the interrupt command is executed, it is returned to the main program and continues to be executed. How does a single-chip microcomputer locate the interrupt program and return it? Let's talk about it later.

The structure of MCS-51 Single Chip Microcomputer Interrupt System:
The symbols, names, and conditions of the five interrupt sources are as follows.
Int0: External Interrupt 0, introduced by the p3.2 port line, caused by low level or lower hop edge.
Int1: External Interrupt 1, which is introduced by the P3.3 port Line and is caused by low-level or lower-hop edges.
T0: Timer/Counter 0 interrupted, caused by t0's full return to zero.
T1: Timer/Counter l interrupt, caused by full return of T1.
Ti/RI: The serial I/O is interrupted, and the serial port is triggered after one frame of characters are sent/received.
The structure of the entire interrupt system is shown in Figure 1.

<51 MCU Interrupt System Structure>

It consists of special function registers, interrupt entry, and sequential query logic circuits related to the interrupt, including five interrupt request sources, the four registers (ie, IP, Econ, and scon) used for interrupt control are used to control interrupt classes, interrupt enabling and shutting down, and determine the priority of various interrupt sources.

Interrupt request source:

(1) external interrupt request Source: namely, the External Interrupt 0 and 1, introduced through the external pin, there are two pins on the microcontroller, the name is int0, int1, p3.2 and P3.3 pins. Four in the internal tcon are related to external interruptions. It0: int0 trigger control bit, which can be used for provisioning and resetting by software, it0 = 0, int0 is a low-level trigger mode, it0 = 1, int0 is a negative hop trigger mode. The difference between the two methods will be discussed later. Ie0: int0 indicates the flag of the interrupted request. When there is an external interrupt request, this will set 1 (this is done by the hardware), after the CPU response is interrupted, the hardware will clear ie0 0. The use of it1 and ie1 is the same as that of it0 and ie0. (2) Internal interrupt request source tf0: The overflow interrupt mark of the timer t0. When the T0 count overflows, the hardware positions tf0. When the CPU response is interrupted, the hardware clears tf0 from 0. TF1: similar to tf0. Ti and RI: sending and receiving interruptions in the serial port. 2. Interrupt allow register ie in the MCS-51 Interrupt System. Interrupt allow or deny is controlled by an eight-bit interrupt in the chip that can be bit addressable. See the following table for eax

EA is the master switch. If it is equal to 0, all interruptions are not allowed. Elasticsearch interrupt allows ET1-timer 1 interrupt to allow ex1-External Interrupt 1 interrupt. Et0-timer 0 interrupt allow ex0-External Interrupt 0 interrupt allow. If we want to set the allow external interrupt 1, the timer 1 interrupt to allow, and other do not allow, ie can be eax

That is, 8ch. Of course, we can also use the bitwise Operation Command SETB EA

SETB et1setb ex1

To implement it. 3. Natural priority of five interrupt sources and interrupt service entry address external interrupt 0: 0003h timer 0: 000bh External Interrupt 1: 0013h timer 1: 001bh Serial Port: h their natural priorities are arranged from high to low. Here, we should understand why we have written some programs as follows:

Org 0000 hljmp start

Org 0030 H

Start :.

The purpose of this writing is to let out the vector address occupied by the interrupt source. Of course, when there is no interruption in the program, there is no mistake in principle to write the program directly starting from mongoh, but it is best to do so in actual work. Priority: the single-chip microcomputer adopts the natural priority and manual setting of high and low priority policies, that is, the programmer can set which interrupts are of high priority and which ones are of low priority, because there are only two levels, some interruptions must be at the same level and at the same level, which is determined by the natural priority.

At startup, each interruption is at a low priority. We can use commands to set the priority. In Table 2, the IP address of the interrupt priority register is set to higher. If the IP address is set to 1, the corresponding interrupt is set to higher priority. Otherwise, the IP address is set to lower priority.

Xx

X

PS

Pt1

Px1

Pt0

Px0

For example, the following requirements are set to set T0 and waiving 1 to a higher priority, and the others to a lower priority, and the IP value is obtained. The first three digits of the IP address are useless. You can set the value to 000 and then write the IP address as required.

Therefore, the final IP value is 06 h. Example: in the preceding example, if five interrupt requests occur at the same time, determine the order of the interrupt response. Response sequence: timer 0-> External Interrupt 1-> External Interrupt 0-> real-time device 1-> serial interrupt.

MCS-51 interrupt response process:

1,Conditions for interrupt response: At this point, we are still amazed at the computer's response to interruptions. We can respond to external events, it is because we have a variety of "sensors"-eyes and ears can accept different information. How can computers do this? In fact, this is not surprising at all. When MCS51 is working, it will query each interrupt mark in every machine cycle to see if they are "1". If it is 1, it indicates that there is an interrupted request, so the so-called interruption is actually a query, but it is only a query in every cycle. For adults, this is equivalent to reading a book. Every second you raise your head and check if someone is ringing the doorbell or has a phone number .... Stupid, isn't it? But computers are like this, and no one is smart at all. After understanding the above interrupt process, it is difficult to solve the conditions for the interrupt response. In one of the following three cases, the CPU will block the response to the interruption:

The CPU is processing an interrupt request at the same level or higher level.

The current machine cycle is not the last cycle of the currently executing command. We know that the single-chip microcomputer has single-cycle, double-cycle, and three-cycle commands. The current command execution is single-byte. If it is dual-byte or four-byte, it is necessary to wait until the entire command is completed, in order to respond to the interruption (because the interruption query may be found in each machine cycle ).

If the command currently being executed is a command that returns a batch order (RETI) or an IP address or Internet Explorer register, the CPU should interrupt at least one command. These are all related to the interruption. If the IP address or IE is being accessed, the interruption may be enabled, disconnected, or the priority of the interruption may be changed. The interrupted return command indicates that the interruption has not been completed, therefore, you must wait until the processing of this command is complete, and then execute another command to respond to the interruption.

2. In the interrupt response process, when the CPU responds to the interrupt, it first sends the address of the next instruction of the Current Instruction (that is, the instruction to be executed after the interrupt is returned) to the stack, and then according to the interrupt mark, send the corresponding interrupt entry address to the PC. The PC is the program pointer, And the CPU takes the command according to the value in the PC and the value in the PC, so the program will go to the interrupt entry to continue execution. These tasks are completed by hardware, so we do not have to consider them. There is another question: have you noticed that each interrupt vector address is separated by only eight units, for example, 0003-000b? How do you complete the interrupt program in such a small space? It's easy. If you arrange an ljmp command at the interrupt point, won't you jump the interrupt program to any place? A complete main program looks like this:

Org 0000 hljmp start

Org 0003 H

Ljmp int0; 0org 000bh

Reti; no timer 0 interrupt, put a reti here, in case of "accidentally" interrupt, there will not be too much consequence ..

After the program is interrupted, you must execute A reti command. After executing this command, the CPU will take out the address stored in the stack and send it back to the PC, then the program will continue to execute from the interruption of the main program. Note: CPU protection is very limited. It only protects one address, while other things are not protected, therefore, if you use a and psw in the main program and use them again in the interrupt program, you must ensure that the data returned to the main program is not interrupted, you have to protect it yourself.

The control register of the interrupt system:
The interrupt system has two control registers, ie and IP, which are used to set the priority of each interrupt source for opening/closing and interruption respectively. In addition, four additional characters in tcon are used to select conditions that cause external interruptions and serve as signs.

1. Interrupt permitted register -- IE
In special function registers, the byte address is a8h, the bit address (from low to high) is A8H-AFH respectively.
The basic format of IE is as follows:

EA: The allowable bits of global interruption. Ea = 0: Disable all interrupts. Ea = 1: enable global interrupt control. Under this condition, the corresponding interrupt control bit determines whether to enable or disable the corresponding interrupt.
×: Invalid bit.
ES: serial I/O interrupt bits. Es = 1. Enable the serial I/O interrupt; es = 0. Disable the serial I/O interrupt.
ETL; Timer/Counter 1 interrupt allowed bit. ETL = 1. Enable T1 interrupt; ETL = O. Disable T1 interrupt.
Exl: The allowable bits of the External Interrupt. Exl = 1, enable int1; exl = 0, disable int1.
Et0: The allowable bit of the timer/Counter 0 interrupt. Et0 = 1, open t0 interrupt; et0 = 0, disable to interrupt.
Exo: The External Interrupt is 0. Ex0 = 1, enable int0; ex0 = 0, disable int0.

Interrupt priority register -- IP:
In special function registers, the byte address is b8h, And the bit address (from low to high) is b8h 1-bfh, respectively. The IP address is used to set which of the two levels of interruptions each interrupt source belongs, the basic IP Format is shown in Figure 3:

×: Invalid bit.
PS: serial I/O interrupt priority control bit. PS = 1, high priority; PS = 0, low priority.
PTL: Timer/Counter 1 interrupt priority control bit. PTL = 1, high priority; PTL = 0, low priority.
Pxl: the priority control bit of the External Interrupt 1. Pxl = 1, high priority; pxl = O, low priority.
Pt0: priority control bit of the timer/Counter o interrupt. Pt0 = 1, high priority; PTO = 0, low priority.
Px0: the priority control bit of the External Interrupt 0. Px0 = 1, high priority; px0 = 0, injury priority.
In the MCS-51 SCM series, high-level interrupt can interrupt low-level interrupt to form interrupt nesting; between the same level interrupt, or low-level advanced interrupt cannot form interrupt nesting. If several same-level interruptions request interrupt responses to the CPU at the same time, the CPU determines the response order in the following order:

Int0 A T0---INT1 T1 RI/T1.

Response Process of Interruption

If an interrupt source is in the open state and meets the conditions for the interrupt response through programming settings, and ① The instruction currently being executed has been executed
1. The current end responds to similar or advanced interruptions
2. If the IP address interrupt control register or the reh command is executed, the microcontroller responds to the interrupt.
Under normal circumstances, from the effective start of the interrupt request signal to the response of the interrupt request, it usually takes three to eight machine cycles. After the interrupt is returned, the interrupt request flag is automatically cleared (for the interrupt flag of the serial I/O port, use software to clear it), and the breakpoint is the value of the program counter (PC) press into the stack (for recovery); then load the corresponding interrupt entry address into the PC, so that the program is transferred to the corresponding interrupt service program for execution.
The interrupt entry addresses of each interrupt source in the program memory are as follows:
Interrupt source entry address
Int0 (External Interrupt 0) 0003 H
Tf0 (to interrupt) 000bh
Int1 (External Interrupt 1) 0013 H
TFL (T1 interrupt) 001bh
RI/Ti (Serial Port interruption) 0023 H
Because the interrupt entry addresses are very close to each other and are not easy to store long interrupt service programs, a transfer instruction is usually arranged in two or three units at the beginning of the interrupt entry address, to be transferred to the interrupted service program arranged there. Take T1 as an example. The process is shown in step 4.
Because each of the five interrupt sources has its own disconnection request flag 0, tf0, IEL, TFL, and RI/Ti, each flag is automatically set to 1 when the interrupt source meets the conditions of the interrupt request, to interrupt the request to the CPU. If the CPU cannot respond immediately after an interrupted SOURCE initiates a request, as long as the request mark is not manually cleared by the software, the status of the request will remain, this process is different from the other four for the interrupt of the serial port until the CPU responds to the interrupt. Even if the CPU responds to the interrupt, the disconnection mark RI/Ti will not be automatically cleared. You must set the instruction to clear the RI/Ti in the interrupt service program before sending an interrupt request again.
The on-site protection and recovery of CPU must be completed by the corresponding response interrupt service program. After executing the rETI interrupt return command, the breakpoint value will automatically pop up from the top 2 bytes of the stack, and load the PC register so that the CPU continues to execute the program that is interrupted.
The following is an example of application timer interruption.
A program is required to set the online output cycle of p1.0 port to 2 ms square wave pulse. MCU crystal oscillator frequency
Fosc = 6 MHz.
1. Method: the timer t0 is used for 1 ms timing. When the timer value is reached, the interruption is triggered. In the interrupted service program, the p1.0 status is reversed and the interval is set to 1 ms again.
2. Initial Values: machine cycle MC = 12/fosc = 2us. Therefore, the number of machine cycles required by timed LMS is D, that is, 0lf4h. If t0 is set to work mode 1 (16-Bit mode), the initial value is (01f4h) for complement = feoch.

Start:
MoV tmod, #01 H
T0 indicates the timer status, and the operation mode is 1.

MoV tl0, # 0ch
; T0 initial low-level timing values

MoV th0, # 0feh
; T0's initial values for high timing

MoV tcon, #10 h
; Open t0

SETB et0
; 1et0, that is, t0 is allowed to be interrupted

SETB EA
; 1 EA, that is, a global interruption

Ajmp $
; Dynamic temporary storage

000bh:
Ajmp ist0
; Transfer to t0 interrupt service program entry address ist0

Ist0:
MoV tl0, # 0ch
; Reset the initial value of the timer

MoV th0, # 0feh
; Reset the initial value of the timer

Cpl p1.0
; P1.0 reverse

Ret1
; Interrupt return

Serial Port Control register:

The serial port has two control registers, scon and pcon, which are used to set the working mode of the serial port, the running status of the receiving/sending, the characteristics of the receiving/sending data, and the baud rate, as well as the mark of the interruption of the operation.
① Serial port control register scon
The Byte address of scon is 98 h, and the bit address (from low to high) is 98h 9fh. Scon format 5 is shown.

SMO, SML:
The control bit of the working mode of the serial port.
00 -- Method 0; 01 -- Method 1;
10 -- method 2; 11 -- Method 3.
SM2:
Only used for multi-host communication control bit in Mode 2 and Mode 3
Sender SM2 = 1 (requires program-controlled setting ).
When it is in method 2 or 3:
When the receiver is SM2 = 1, if rb8 = 1, the serial reception interruption may occur. If rb8 = 0, no
This causes the interruption of the serial reception. When SM2 is set to 0, if rb8 is set to 1, the serial reception interruption may occur.
Rb8 = 0, can also cause the interruption of serial reception.
Ren:
Serial receiving allowed bits.
0 -- prohibit receiving; 1 -- allow receiving.
Tb8:
In method 2 and 3, tb8 is the 9th-bit data to be sent by the sender.
Rb8:
In method 2 and 3, rb8 is the 9th-bit data received by the receiver.
Tb8.
Ti:
Indicates the sending interruption flag. The software must be cleared before sending. Ti remains at zero level during sending,
After sending a frame of data, the hardware automatically sets the value to 1. If you want to resend it, you must use the software to reset it.
RI:
The receiving interrupt flag. Before receiving, the software must be used for resetting, and the RI must maintain zero power during the receiving process.
After receiving a frame of data, the on-chip hardware automatically sets it to 1. If you want to receive it again, you must use software.
Reset again.

Power Control Register pcon

Pcon has a byte address of 87 h, which is a non-bitwise address, as shown in pcon format 6. It should be noted that pcon has several effective control bits for the 80C31 microcontroller.

Smod: doubles the baud rate. When calculating the baud rate of the serial mode 1, 2, 3, 0 --- do not double; 1 --- double.

Application features of serial interrupt:

The serial I/O port of the 8031 microcontroller is an interrupt source, which has two interrupt signs RI and Ti, RI for receiving, and Ti for sending.
No matter how the serial port works, Ti/Ri must be cleared before sending/receiving. After a frame of data is sent/received, Ti/Ri is set to 1 automatically. To send/receive data again, you must clear it with software.
When a serial interrupt is enabled, for methods 0 and 1, after a frame of data is sent/received, in addition to setting Ti/RI, it will also cause a serial interrupt request, and execute the program. However, for receivers in Mode 2 and Mode 3, you must check the status of SM2 and rb8 to determine whether the Ri is set and whether the opening of the serial interrupt is Enabled:
SM2 rb8 receiver interrupt mark and interrupt status
0 1 activate Ri, causing interruption
1 0 no activation Ri, no interruption
1. Activate Ri, causing interruption
The single-chip microcomputer utilizes the characteristics of method 2 and 3 to realize communication between multiple machines. Common application methods of serial ports can be found in the relevant sections.

Determine the baud rate:

For method 0, the baud rate has been fixed to fosc/12. The baud rate varies with the frequency of the external crystal oscillator. The commonly used fosc has 12 MHz and 6 MHz, so the baud rate is 1000x103 and 500x103/s. In this mode, the data will be automatically sent/received at a fixed baud rate, and you do not need to set it at all.
For method 2, the baud rate is calculated as 2smod-fosc/64. When smod is set to 0, the baud rate is FM/64. When smod is set to 1, the baud rate is fosc/32. In this way, the baud rate is determined after the smod bit state is set by the program control, and no additional settings are required.
For methods 1 and 3, the baud rate is calculated as 2 smod/32 × T1 overflow rate. Depending on the smod status bit, the baud rate can be TL/32 overflow rate or t1/16 overflow rate. Because the T1 overflow rate is easy to set, the baud rate is very flexible.
Previously described, the timer TL has four working modes. In order to get its overflow rate, and do not have to enter the interrupted service program, T1 is usually set to the running status of the Working Mode 2, that is, the time constant is automatically added to 8 bits. In this way, the overflow rate (times/s) of T1 can be calculated as follows:

The following section of the main program and interrupt service program is a program that uses the serial method l to continuously send a piece of data from the continuous increase of the Earth starting from the data for H. The frequency of the single-chip microcomputer crystal oscillator is 6 MHz, and the baud rate is 1200 bits/s.

Org 2000 h
; Initial timer values of 1200 bits/s

MoV TL1, # 0f3h

MoV Th1, # 0f3h
; Make smod = 0

MoV pcon, #00 h
; T1 Mode 2

MoV tmod, #20 h

SETB EA

CLR ET1
; Disable T1 interruption

SETB es
; Enable serial interrupt

SETB tr1
; Enable T1 timing

MoV scon, #40 h
; Serial mode 1

CLR

MoV sbuf,
; Serial Transmission

JNB T1, $
; Waiting for sending

CLR T1,
; Clear sign

Sjmp $

Org 0023 H
; Serial interrupt entry address

MoV sbuf,
; Continuous transmission

JNB T1, $

INC

CLR T1

Ret1
; Interrupt return