MCU software analog SPI interface-deep understanding of SPI bus protocol

MCU simulation SPI interface-deep understanding of SPI bus protocol SPI (serial peripheral interfacer serial peripheral interface) is a synchronous serial communication interface launched by Motorola, the serial connection between the microprocessor compaction controller and the peripheral extended chip has developed into an industrial standard. Currently, various semiconductor companies have released a large number of chips with SPI interfaces with various functions, such as Ram, EEPROM, flashrom, a/D converter, D/A converter, led/LED display driver, I/O interface chip, real-time clock, UART transceiver, etc, it provides users with extremely flexible and inexpensive options for peripheral expansion. Because the SPI bus interface only occupies four I/O Ports of the microprocessor, the SPI bus interface can simplify the circuit design and save many interface devices and I/O Ports in the Conventional Circuit, improve design reliability.

The simulation of Serial EEPROM 93ca6 by using single-chip microcomputer 5l is used as an example. 1 shows how to use the I/O port of single-chip microcomputer to simulate SPI bus through software. Here, we will only introduce the time sequence of the read command and the application subroutine. Working principle of 93c46 memory SPI bus

93ca6 acts as the slave device, and its SPI interface uses four I/O Ports: serial clock lines (SK), output data line do, input data line Di, and high level valid slave machine select line CS. Its data transmission format is high (MSB) before, low (LSB) after. The timing of the SPI bus interface reading command of 93c46 is shown in 2.
Implementation of software simulation SPI interface

For a single-chip computer that does not have an SPI serial bus interface, you can use software to simulate the SPI operation. Figure 1 shows the hardware connection diagram between the single-chip microcomputer and the serial EEPROM 93c46, p1.0 simulates the SDO at the data output end of the SPI main device, p1.2 simulates the sck at the SPI clock output end, p1.3 simulates the SCS at the SPI slave terminal, and p1.1 simulates the SPI data input SDI.
After power-on reset, set the initial status of p1.2 (sck) to 0 (idle ).
Read operation: the first step is to send a 1-bit start bit (1), a 2-bit operation code (10), and a 6-bit read data address (a5a4a3a2a1a0) through the p1.0 port ), then read 1-bit space (0) through the p1.1 port, and then read the l6-bit data (before the high position ).
Write operation: the first step is to send 1-bit start bit (1), 2-bit operation code (01), and 6-bit written data address (a5a4a3a2a1a0) through the p1.0 port ), then, the written L6-bit data is sent through the p1.0 port. Before the write operation, the write permission command must be sent. After the write operation, the write prohibition command must be sent.
Write permitted operation (Wen): The write operation first sends one start bit (1), two operation codes (00), and six data records (11 XXXX ). Write prohibition (WDS): The write operation first sends one start bit (1), two operation codes (00), and six data records (00 XXXX ).
The following describes the subprograms used to simulate SPI with C51.

// First define the I/O port sbit SDO = p1 ^ 0; sbit SDI = p1 ^ 1; sbit sck = p1 ^ 2; sbit SCS = p1 ^ 3; sbit acc_7 = ACC ^ 7; unsigned int spiread (unsigned char add) {unsigned char I; unsigned int datal6; add & = 0x3f; /* 6-bit address */Add | = 0x80;/* read operation code l0 */SDO = 1;/* send 1 as the start position */sck = 0; sck = 1; for (I = 0; <8; I ++)/* Send operation code and address */{If (add & 0x80 = 1) SDO = 1; else SDO = 0; sck = 0;/* receive data from the rising edge of the device */sck = 1; add <= 1;} sck = 1; /* send data after the device clock line drops along, empty read 1 bit data */sck = 0; datal6 <= 1; /* read 16-Bit Data */for (I = 0; <16; I ++) {sck = 1; _ NOP _ (); If (SDI = 1) datal6 | = 0x01; sck = 0; datal6 <= 1;} return datal6 ;}

For peripheral chips with different serial interfaces, their clock sequence is different. The subroutine above is a device for the input (received) data on the rising edge of the sck and output (sent) data on the falling edge. These subprograms are also applicable to the rising edge input and falling edge output of the serial peripheral interface chip, as long as the program changes p1.2 (sck) to adjust the output level order.